Abstract: Provided in the present disclosure is a preparation method for 1-[2-chloro-3-(bromomethyl)-4-(methylsulfonyl)phenyl]ethanone. A preparation method for 2-chloro-3-(trifluoroethoxymethyl)-4-(methylsulfonyl)benzoic acid of the present disclosure comprises: (1) in the presence of an initiator, subjecting 1-[2-chloro-3-(methyl)-4-(methylsulfonyl)phenyl]ethanone to a bromination reaction to obtain 1-[2-chloro-3-(bromomethyl)-4-(methylsulfonyl)phenyl]ethanone; (2) reacting 1-[2-chloro-3-(bromomethyl)-4-(methylsulfonyl)phenyl]ethanone to obtain 1-[2-chloro-3-(trifluoroethoxymethyl)-4-(methylsulfonyl)phenyl]ethanone; and (3) preparing 2-chloro-3-(trifluoroethoxymethyl)-4-(methylsulfonyl)benzoic acid from 1-[2-chloro-3-(trifluoroethoxymethyl)-4-(methylsulfonyl)phenyl]ethanone.

Abstract: A fan lamp includes a driving mechanism, a lamp panel, a driving circuit board, and light sources. The driving mechanism is used for driving the fan lamp to rotate, and includes a driving shaft, a housing that is rotatably sleeved on the driving shaft, and a mounting cavity being formed inside the housing; the lamp panel is connected to the driving mechanism; the driving circuit board is mounted on the side of the lamp panel facing the driving mechanism; the light sources are used for illumination and are mounted on the side of the lamp panel facing away from the driving mechanism; and the driving circuit board is used for driving the light sources and the driving mechanisms to be turned on/off.

Abstract: A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.

Abstract: A semiconductor device and a method are provided. The semiconductor device includes a substrate, first and second transistors, and a first isolation structure. The first isolation structure is between source/drain regions of the second transistor and source/drain regions and/or channel region of the first transistor. An active structure of the second transistor has a length less than that of an active structure of the first transistor, and/or the active structure of the second transistor has a width less than that of the active structure of the first transistor. At least one pair of adjacent source/drain contact structures belonging to the first and second transistors and located on the same side in the length direction of the gate stack structures are spaced apart, and the source/drain contact structures of the first and second transistors are in a vertical space of a region where the first and second transistors are located.

Abstract: The present application provides a magnetic component, an integrated magnetic device and a three-phase converter. The magnetic component includes first to fourth side legs. The first side leg is located between a first center leg and a second center leg, and a side of the part of the first side leg away from the third center leg, respectively. The second side leg is located between the second center leg and the third center leg, and a side of the part of the second side leg away from the first center leg, respectively. A part of the third side leg located at the second side of the first center leg, and a part of the fourth side leg located at a first side of the third center leg.

Abstract: The semiconductor device includes: a semiconductor base substrate, and a gate-all-around transistor disposed on the semiconductor base substrate, where the gate-all-around transistor includes a channel region, a source/drain region, a gate stack structure, an inner spacer, and a conductive semiconductor structure; the source/drain region is disposed on both sides of the channel region in a length direction; the gate stack structure surrounds a periphery of the channel region; the inner spacer is disposed between the gate stack structure and the source/drain region; and the conductive semiconductor structure is disposed at least between the channel region and the source/drain region, at least a partial region of the conductive semiconductor structure overlaps with at least a partial region of the inner spacer in a length direction of the gate stack structure, and there is an interface between the conductive semiconductor structure and the channel region.

Abstract: A fan lamp includes a driving mechanism, a lamp panel, a driving circuit board, and light sources. The driving mechanism is used for driving the fan lamp to rotate; the lamp panel is connected to the driving mechanism; the driving circuit board is mounted on the side of the lamp panel facing the driving mechanism; the light sources are used for illumination and are mounted on the side of the lamp panel facing away from the driving mechanism; and the driving circuit board is used for driving the light sources and the driving mechanisms to be turned on/off.

Abstract: A series of pharmaceutical compositions containing polypeptide dual agonist compounds and pharmaceutically acceptable salts thereof, wherein same have dual agonist effects on a human glucagon-like peptide-1 (GLP-1) receptor and a human blood glucose-dependent insulinotropic polypeptide (GIP) receptor, and can be used for treating non-insulin-dependent diabetes, insulin-dependent diabetes, obesity and other related diseases.

Abstract: A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.

Abstract: The present disclosure relates to a vertical channel SRAM cell, a method of manufacturing the same, a memory, and an electronic device, which pertain to a field of semiconductor technology. The vertical channel SRAM cell includes: a pull-up transistor device layer; an intermediate spacer layer on the pull-up transistor device layer; and a pull-down transistor device layer separated from the pull-up transistor device layer by the intermediate spacer layer, where the pull-down transistor device layer includes a pull-down transistor and a pass gate transistor; where the pass gate transistor is connected with the pull-down transistor by an upper source layer at identical height; the first pull-up transistor and the first pull-down transistor form a first inverter, the second pull-up transistor and the second pull-down transistor form a second inverter, and the first inverter and the second inverter are coupled to each other through a metal gate strip.

Abstract: The present disclosure discloses a method and a system for controlling a switching power supply, the switching power supply comprising a power factor correction circuit which comprises at least one electrolytic capacitor, the method comprising: detecting a ripple voltage of the electrolytic capacitor; controlling an actual output power of the switching power supply to be equal to a reference output power based on the ripple voltage of the electrolytic capacitor, wherein the reference output power equals to a compensated output power or an upper limit output power, and wherein the compensated output power is obtained by comparing the ripple voltage of the electrolytic capacitor with a reference voltage and subjecting to a compensation calculation. The reference output power is a smaller one of the compensated output power and the upper limit output power.

Abstract: The present disclosure provides a method of repairing an integrated circuit, which relates to a field of integrated circuit technology. The method of repairing the integrated circuit includes: providing an integrated circuit to be repaired; acquiring a first performance-related parameter and a performance degradation-related parameter of the integrated circuit to be repaired, and establishing a circuit aging model; simulating the integrated circuit to be repaired, and determining the transistor to be repaired in the integrated circuit to be repaired and its first pre-failure duration; acquiring a second performance-related parameter of the transistor to be repaired; determining a repair parameter corresponding to the transistor to be repaired; and repairing the transistor to be repaired according to the first pre-failure duration and the repair parameter by using a gate-induced drain leakage current repair method.

Abstract: The present disclosure discloses a fan blade structure, a fan and a fan lamp. A fan blade structure includes: an inner edge located at a windward side, where the inner edge at least partially protrudes towards a leeward side, and the inner edge extends obliquely upwards from one end of the fan blade structure close to a rotational axis to one end of the fan blade structure facing away from the rotational axis; an outer edge located at the leeward side as a boundary edge of the fan blade, where the outer edge protrudes towards the leeward side, and the outer edge extends obliquely upwards from the end of the fan blade structure close to the rotational axis to the end of the fan blade structure facing away from the rotational axis; and a cambered surface connected between the inner edge and the outer edge.

Abstract: A cyclin modulator, specifically a compound of formula (I) or a pharmaceutically acceptable salt thereof are provided.

Abstract: The present disclosure discloses a method for manufacturing an oxide layer and a semiconductor device, which pertain to the field of semiconductor technology. The method for manufacturing the oxide layer includes: providing a semiconductor structure; forming a first oxide layer on the semiconductor structure in a first low-temperature environment; applying an oxygen plasma treatment on the first oxide layer and a part of the semiconductor structure in a second low-temperature environment, so that the first oxide layer is formed into a second oxide layer, where a compactness of the second oxide layer is greater than a compactness of the first oxide layer. The semiconductor device includes a semiconductor structure and a second oxide layer disposed on the semiconductor structure, where the second oxide layer is manufactured and formed using the aforementioned oxide layer fabrication method.

Abstract: A fan blade, a fan and a fan lamp. The fan blade includes: a blade root; a blade tip; a leading edge, which connects the blade root to the blade tip and is located on a windward side; and a trailing edge, which connects the blade root to the blade tip and is located on a leeward side, wherein the leading edge is configured in a wavy shape from the blade root towards the blade tip, the trailing edge is configured in an arc shape, and the distance between the leading edge and the trailing edge increases first and then decreases from the blade root towards the blade tip.

Abstract: The present disclosure provides a pulse width modulation method, which is applied to a bridge circuit, comprising: configuring a first driving mode and a second driving mode of the pulse width modulation of the bridge circuit, wherein losses of the same switch of the bridge circuit in the first driving mode and the second driving mode are reversed; in a first time window, controlling the bridge circuit to operate in the first driving mode, wherein the first time window is M switching cycles, and M is a positive integer; and in a second time window, controlling the bridge circuit to operate in the second driving mode, wherein the second time window is N switching cycles, N is a positive integer, and the pulse width modulation process of the bridge circuit is divided into the first time window and the second time window that are alternated cyclically.

Abstract: The semiconductor device includes a base substrate, first and second layer semiconductor structures, first and second contact structures. The second layer semiconductor structure is arranged above the first layer semiconductor structure at intervals along a thickness direction of the base substrate. The first contact structure is arranged in the base substrate and includes a first contact portion in electrical contact with a first source/drain region included in the transistor in the first layer semiconductor structure and a second contact portion in electrical contact with a first gate stack structure. The second contact structure is arranged on a side of the second layer semiconductor structure away from the first layer semiconductor structure and includes a third contact portion in electrical contact with a second source/drain region included in the transistor in the second layer semiconductor structure and a fourth contact portion in electrical contact with a second gate stack structure.

Abstract: Ceiling assemblies and a fan lamp are provided. The ceiling assembly is configured for an installation of a fan lamp, and includes: a bracket body and a ceiling box, wherein the ceiling box has an installation cavity, and the bracket body is housed in the installation cavity, the ceiling box is provided with a first connecting part, the bracket body is provided with a second connecting part at a position corresponding to the first connecting part, the first connecting part is detachably connected with the second connecting part, the first connecting part is provided with a first guiding part on a connecting surface thereof corresponding to the second connecting part, and the first connecting part and the second connecting part are rotatably snap connected through the first guiding part.

Abstract: The present disclosure discloses a fan blade structure, a fan and a fan lamp, belonging to the field of household appliances. A fan blade structure includes: an inner edge located at a windward side, where the inner edge at least partially protrudes towards a leeward side, and the inner edge extends obliquely upwards, gradually, from one end of the fan blade structure close to a rotational axis to one end of the fan blade structure facing away from the rotational axis; an outer edge located at the leeward side, where the outer edge protrudes towards the leeward side, and the outer edge extends obliquely upwards from the end of the fan blade structure close to the rotational axis to the end of the fan blade structure facing away from the rotational axis; and a cambered surface connected between the inner edge and the outer edge.