Abstract: A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.

Abstract: The present disclosure relates to a vertical channel SRAM cell, a method of manufacturing the same, a memory, and an electronic device, which pertain to a field of semiconductor technology. The vertical channel SRAM cell includes: a pull-up transistor device layer; an intermediate spacer layer on the pull-up transistor device layer; and a pull-down transistor device layer separated from the pull-up transistor device layer by the intermediate spacer layer, where the pull-down transistor device layer includes a pull-down transistor and a pass gate transistor; where the pass gate transistor is connected with the pull-down transistor by an upper source layer at identical height; the first pull-up transistor and the first pull-down transistor form a first inverter, the second pull-up transistor and the second pull-down transistor form a second inverter, and the first inverter and the second inverter are coupled to each other through a metal gate strip.

Abstract: The present disclosure discloses a method and a system for controlling a switching power supply, the switching power supply comprising a power factor correction circuit which comprises at least one electrolytic capacitor, the method comprising: detecting a ripple voltage of the electrolytic capacitor; controlling an actual output power of the switching power supply to be equal to a reference output power based on the ripple voltage of the electrolytic capacitor, wherein the reference output power equals to a compensated output power or an upper limit output power, and wherein the compensated output power is obtained by comparing the ripple voltage of the electrolytic capacitor with a reference voltage and subjecting to a compensation calculation. The reference output power is a smaller one of the compensated output power and the upper limit output power.

Abstract: The present disclosure provides a method of repairing an integrated circuit, which relates to a field of integrated circuit technology. The method of repairing the integrated circuit includes: providing an integrated circuit to be repaired; acquiring a first performance-related parameter and a performance degradation-related parameter of the integrated circuit to be repaired, and establishing a circuit aging model; simulating the integrated circuit to be repaired, and determining the transistor to be repaired in the integrated circuit to be repaired and its first pre-failure duration; acquiring a second performance-related parameter of the transistor to be repaired; determining a repair parameter corresponding to the transistor to be repaired; and repairing the transistor to be repaired according to the first pre-failure duration and the repair parameter by using a gate-induced drain leakage current repair method.

Abstract: The present disclosure discloses a fan blade structure, a fan and a fan lamp. A fan blade structure includes: an inner edge located at a windward side, where the inner edge at least partially protrudes towards a leeward side, and the inner edge extends obliquely upwards from one end of the fan blade structure close to a rotational axis to one end of the fan blade structure facing away from the rotational axis; an outer edge located at the leeward side as a boundary edge of the fan blade, where the outer edge protrudes towards the leeward side, and the outer edge extends obliquely upwards from the end of the fan blade structure close to the rotational axis to the end of the fan blade structure facing away from the rotational axis; and a cambered surface connected between the inner edge and the outer edge.

Abstract: A cyclin modulator, specifically a compound of formula (I) or a pharmaceutically acceptable salt thereof are provided.

Abstract: The present disclosure discloses a method for manufacturing an oxide layer and a semiconductor device, which pertain to the field of semiconductor technology. The method for manufacturing the oxide layer includes: providing a semiconductor structure; forming a first oxide layer on the semiconductor structure in a first low-temperature environment; applying an oxygen plasma treatment on the first oxide layer and a part of the semiconductor structure in a second low-temperature environment, so that the first oxide layer is formed into a second oxide layer, where a compactness of the second oxide layer is greater than a compactness of the first oxide layer. The semiconductor device includes a semiconductor structure and a second oxide layer disposed on the semiconductor structure, where the second oxide layer is manufactured and formed using the aforementioned oxide layer fabrication method.

Abstract: A fan blade, a fan and a fan lamp. The fan blade includes: a blade root; a blade tip; a leading edge, which connects the blade root to the blade tip and is located on a windward side; and a trailing edge, which connects the blade root to the blade tip and is located on a leeward side, wherein the leading edge is configured in a wavy shape from the blade root towards the blade tip, the trailing edge is configured in an arc shape, and the distance between the leading edge and the trailing edge increases first and then decreases from the blade root towards the blade tip.

Abstract: The present disclosure provides a pulse width modulation method, which is applied to a bridge circuit, comprising: configuring a first driving mode and a second driving mode of the pulse width modulation of the bridge circuit, wherein losses of the same switch of the bridge circuit in the first driving mode and the second driving mode are reversed; in a first time window, controlling the bridge circuit to operate in the first driving mode, wherein the first time window is M switching cycles, and M is a positive integer; and in a second time window, controlling the bridge circuit to operate in the second driving mode, wherein the second time window is N switching cycles, N is a positive integer, and the pulse width modulation process of the bridge circuit is divided into the first time window and the second time window that are alternated cyclically.

Abstract: The semiconductor device includes a base substrate, first and second layer semiconductor structures, first and second contact structures. The second layer semiconductor structure is arranged above the first layer semiconductor structure at intervals along a thickness direction of the base substrate. The first contact structure is arranged in the base substrate and includes a first contact portion in electrical contact with a first source/drain region included in the transistor in the first layer semiconductor structure and a second contact portion in electrical contact with a first gate stack structure. The second contact structure is arranged on a side of the second layer semiconductor structure away from the first layer semiconductor structure and includes a third contact portion in electrical contact with a second source/drain region included in the transistor in the second layer semiconductor structure and a fourth contact portion in electrical contact with a second gate stack structure.

Abstract: Ceiling assemblies and a fan lamp are provided. The ceiling assembly is configured for an installation of a fan lamp, and includes: a bracket body and a ceiling box, wherein the ceiling box has an installation cavity, and the bracket body is housed in the installation cavity, the ceiling box is provided with a first connecting part, the bracket body is provided with a second connecting part at a position corresponding to the first connecting part, the first connecting part is detachably connected with the second connecting part, the first connecting part is provided with a first guiding part on a connecting surface thereof corresponding to the second connecting part, and the first connecting part and the second connecting part are rotatably snap connected through the first guiding part.

Abstract: The present disclosure discloses a fan blade structure, a fan and a fan lamp, belonging to the field of household appliances. A fan blade structure includes: an inner edge located at a windward side, where the inner edge at least partially protrudes towards a leeward side, and the inner edge extends obliquely upwards, gradually, from one end of the fan blade structure close to a rotational axis to one end of the fan blade structure facing away from the rotational axis; an outer edge located at the leeward side, where the outer edge protrudes towards the leeward side, and the outer edge extends obliquely upwards from the end of the fan blade structure close to the rotational axis to the end of the fan blade structure facing away from the rotational axis; and a cambered surface connected between the inner edge and the outer edge.

Abstract: A power switching circuit includes a driving signal part, a first switch element, a second switch element, a first driving circuit and a second driving circuit. The first driving circuit includes a first resistor and a first connection branch, which are connected between a positive driving signal terminal of the driving signal part and a first driving terminal of the first switch element, respectively. The second driving circuit includes a third resistor and a second connection branch, which are connected between the positive driving signal terminal and the second driving terminal of the second switch element, respectively. In a same switching cycle, the turn-on time of the first switch element is earlier than the turn-on time of the second switch element and the turn-off time of the first switch element is earlier than the turn-off time of the second switch element.

Abstract: The present disclosure provides a ceiling assembly and a fan lamp, the ceiling assembly is configured for an installation of a fan lamp, and including: a bracket body and a ceiling box, wherein the ceiling box has an installation cavity, and the bracket body is housed in the installation cavity, the ceiling box is provided with a first connecting part, the bracket body is provided with a second connecting part at a position corresponding to the first connecting part, the first connecting part is detachably connected with the second connecting part, and the first connecting part is provided with a first guiding part on a connecting surface thereof corresponding to the second connecting part.

Abstract: Provided herein are GPX4 inhibitors, e.g., a compound of Formula (I), and pharmaceutical compositions thereof. Also provided herein are methods of their use for treating, preventing, or ameliorating one or more symptoms of a GPX4-mediated disorder, disease, or condition.

Abstract: Provided in the present invention is a small molecule compound, which is characterized in that it is a compound or a stereoisomer, geometric isomer, tautomer, racemate, hydrate, solvate, metabolite, and pharmaceutically acceptable salt or prodrug of the compound as represented by the following structural formula: formula (I). The small molecule compound of the present invention is applicable as a highly efficient and specific JAK kinase inhibitor, specifically a Tyk2 inhibitor and/or a JAK1 inhibitor, and/or a JAK1/Tyk2 dual inhibitor.

Abstract: A Static Random Access Memory (SRAM) cell, a method of manufacturing an SRAM cell, a memory including such SRAM cell and an electronic device are provided. The SRAM cell includes: a substrate; first and second pull-up transistors, first and second pass-gate transistors at substantially a same height relative to the substrate; and first and second pull-down transistors at substantially a same height relative to the substrate, where the first pull-down transistor is stacked on the first pull-up transistor, and the second pull-down transistor is stacked on the second pull-up transistor, where an active region of each of the first and second pull-up transistors, the first and second pull-down transistors, the first and second pass-gate transistors includes a first source/drain layer, a channel layer and a second source/drain layer sequentially disposed in a vertical direction, and the channel layer is in a form of a vertical nanosheet.

Abstract: Disclosed are a pressure control method and a pressure control device for a braking cylinder of a rail vehicle, and the rail vehicle. The method includes the following steps: acquiring the air charge-release volume of the braking cylinder of the rail vehicle and the air flowrate of the braking cylinder; determining the charge-release duration according to the air charge-release volume of the braking cylinder and the air flowrate of the braking cylinder, and controlling the charge-release working duration of the air charge-release solenoid valve according to the air charge-release duration; when the working duration of the air charge-release solenoid valve reaches the charge-release duration, acquiring the predictive pressure of the braking cylinder, and controlling the working state of the air charge-release solenoid valve according to the predictive pressure.

Abstract: A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.

Abstract: A fan blade, a fan and a fan lamp. The fan blade includes: a blade root; a blade tip; a leading edge, which connects the blade root to the blade tip and is located on a windward side; and a trailing edge, which connects the blade root to the blade tip and is located on a leeward side, wherein the leading edge is configured in a wavy shape from the blade root towards the blade tip, the trailing edge is configured in an arc shape, and the distance between the leading edge and the trailing edge increases first and then decreases from the blade root towards the blade tip.