Patents by Inventor Xiaoling Wang

Xiaoling Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12581641
    Abstract: A memory cell includes a transistor, a storage node contact and a capacitor that are connected sequentially, wherein the capacitor includes a lower electrode, an upper electrode and a dielectric layer disposed between the lower electrode and the upper electrode. The lower electrode includes: a first electrode layer having a first sub-electrode region and a plurality of second sub-electrode regions connected to the first sub-electrode region, where the first sub-electrode region is in contact with a surface of the storage node contact, each of the second sub-electrode regions extends along a direction away from the storage node contact and has a first end face and a second end face facing each other in an extension direction, the first end face being in contact with the surface of the storage node contact; and a second electrode layer, covering at least part of a surface of the first electrode layer.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: March 17, 2026
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi Wu, Xiaoling Wang
  • Publication number: 20260051387
    Abstract: Methods, apparatuses, and systems for determining a peritoneal transport status classification of a patient based on mass analyzing low volumes of peritoneal dialysis (PD) effluent evaluated using PD effluent fingerprints of known transport statuses to determine a peritoneal transport status classification of the patient are described. In one example, a method includes obtaining a volume of PD effluent of the dialysis patient, generating patient information via mass analysis of the volume of PD effluent, and determining patient profile information based on evaluating the patient information with a profile library, the patient profile information comprising a peritoneal transport status classification.
    Type: Application
    Filed: August 15, 2025
    Publication date: February 19, 2026
    Applicant: Fresenius Medical Care Holdings, Inc.
    Inventors: Nadja Grobe, Peter Kotanko, Xiaoling Wang
  • Patent number: 12543480
    Abstract: The present disclosure provides a display module and a display device. The display module includes: a circuit board including a first surface and a second surface opposite to the first surface; a display substrate on the first surface of the circuit board; a first glue layer on the first surface of the circuit board and surrounding the a sidewall of the display substrate; and a second glue layer on the second surface of the circuit board, wherein a transparency of the second glue layer is different from a transparency of the first glue layer.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 3, 2026
    Assignees: Yunnan Invensight Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Jinhua Zhang, Shucheng Yang, Dongdong Duan, Jie Sun, Xiaojun Mao, Peng Dong, Bingjie Du, Linhong Yang, Lei Wang, Xiuwen Wang, Xiaoling Wang, Yunlong Ma, Xiong Tao, Ya Lv
  • Patent number: 12522745
    Abstract: A hydrophilic anti-fog nano paint for endoscope is provided. The paint includes, in parts by weight, 1-10 parts of plant polyphenols, 0.1-2 parts of metal ions, 0.1-0.5 parts of biomass molecules, 10-20 parts of additives and 250 parts of solvents. When coated on a substrate surface and dried, the paint forms a coating in which the plant polyphenols and metal ions combine to form a plant polyphenol-metal nano complex. Together with biomass molecules, the plant polyphenol-metal nano complex produces a hydrophilic nanofilm on the laparoscope surface, thereby enhancing the hydrophilicity of the lens interface.
    Type: Grant
    Filed: July 2, 2023
    Date of Patent: January 13, 2026
    Assignee: CHENGDU HONGBO JIAYUAN BIOTECHNOLOGY CO., LTD
    Inventors: Xun Zheng, Zhihui Li, Junling Guo, Yunxiang He, Xiaoling Wang
  • Publication number: 20260006769
    Abstract: A method for manufacturing a semiconductor structure includes: providing a base substrate and forming isolation structures inside the base substrate, where the isolation structures are disposed apart from each other; forming a stacked structure on the base substrate, where the stacked structure is formed by alternately stacking first layers and second layers in a third direction; forming stack openings, where the stack openings pass through the stacked structure along the third direction; forming first base substrate openings, where one of the stack openings and one of the first base substrate openings compose one of first openings; removing parts of the second layers to form second openings, and etching the first base substrate openings to form base substrate openings, where one of the stack openings, one of the base substrate openings, and some of the second openings together compose one of combined openings; and forming capacitor structures in the combined openings.
    Type: Application
    Filed: November 27, 2024
    Publication date: January 1, 2026
    Applicant: CXMT Corporation
    Inventors: Zhipeng ZHAO, Xiaoling WANG, Qiong LUO
  • Patent number: 12513883
    Abstract: A semiconductor structure and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate; etching the substrate to form multiple active areas, trenches each positioned between adjacent active areas, and air gaps positioned below the active areas; and forming a filler layer filling at least each of the trenches.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 30, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jingwen Lu, Xiaoling Wang
  • Publication number: 20250332257
    Abstract: Disclosed in the present application are the use of an antigen short peptide in screening a drug for treating HPV-related diseases and a TCR screened by same, wherein the amino acid sequence of the antigen short peptide is as shown in SEQ ID NO: 1 or SEQ ID NO: 2. In the present application, the antigen short peptide can be used to screen a specific T cell receptor (TCR), and the T cell transduced with the TCR can be specifically activated and have a very strong killing effect on tumor cells expressing A1101 and HPV, which can be used for immunotherapy of HPV positive tumors, such as cervical cancer. In addition, the T cell transduced with the TCR of the present application has a strong activation reaction on a cell line expressing E6, has no activation reaction on a cell line not expressing E6, and has a very strong killing function on the cell line expressing E6 and can effectively inhibit the growth of E6 positive tumors.
    Type: Application
    Filed: May 9, 2023
    Publication date: October 30, 2025
    Applicant: GUANGZHOU MEDICAL UNIVERSITY
    Inventors: Lin CHEN, Xiaoling WANG
  • Publication number: 20250325667
    Abstract: The present application discloses a use of an antigen short peptide in the screening of a drug for treating an HPV-related disease, and a T cell receptor (TCR) screened by the antigen short peptide. An amino acid sequence of the antigen short peptide is represented by SEQ ID NO: 1. The antigen short peptide of the present application can screen a specific TCR, T cells transduced with the TCR can be specifically activated and have a strong killing effect on tumor cells which express A1101 and HPV, and the TCR can be used for immunotherapy of HPV-positive tumors such as cervical cancer. Moreover, the T cells transduced with the TCR of the present application have a strong activation reaction on a cell line which expresses E7, have no activation reaction on a cell line which does not express E7, have a very strong killing function on the cell line which expresses E7, and can effectively inhibit the growth of E7-positive tumors.
    Type: Application
    Filed: May 9, 2023
    Publication date: October 23, 2025
    Applicant: GUANGZHOU MEDICAL UNIVERSITY
    Inventors: Lin CHEN, Xiaoling WANG
  • Patent number: 12396157
    Abstract: A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: August 19, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xiaoling Wang, Hai-Han Hung, Min-Hui Chang
  • Publication number: 20250248986
    Abstract: The present disclosure provides an antifungal drug inhalation formulation, comprising: crystalline nanoparticles of a triazole antifungal drug. The present disclosure further provides a preparation method and use of the antifungal drug inhalation formulation.
    Type: Application
    Filed: February 6, 2025
    Publication date: August 7, 2025
    Inventors: Yuting JIN, Yihua WANG, Dengjun CHEN, Xiaoling WANG, Xiao WANG, Qiongxia XIE
  • Patent number: 12356602
    Abstract: A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: July 8, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng Yang, Xiaojie Li, Xiaoling Wang
  • Publication number: 20250170094
    Abstract: The present disclosure provides a pharmaceutical formulation, wherein raw materials for formulating the pharmaceutical formulation comprise: an active ingredient which is one selected from the group consisting of peramivir, zanamivir, laninamivir, and hydrates or solvates thereof; a carboxylic acid anion donor which is at least one selected from the group consisting of pamoic acid and hydroxynaphthoic acid; and a first pH regulator which is an alkaline pH regulator.
    Type: Application
    Filed: August 22, 2024
    Publication date: May 29, 2025
    Applicant: Hefei Cosource Pharmaceuticals Co., Ltd
    Inventors: Jun Zhang, Dengjun Chen, Yuting Jin, Liuyu Shi, Xiao Wang, Xiaoling Wang, Lixia Ke, Weichen Zhou, Xiaorong Lu
  • Patent number: 12315795
    Abstract: The present application provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure includes: providing a base, the base including a substrate and a first dielectric layer on the substrate; forming a through silicon via in the base, the through silicon via penetrating through the first dielectric layer, extending into the substrate, and having a depth less than a thickness of the base; forming an electrically conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounding the electrically conductive structure, exposing a sidewall of the electrically conductive structure and a part of the substrate, and having a stepwise sidewall; and forming a thermally conductive structure in the filling hole.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: May 27, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Luguang Wang, Xiaoling Wang
  • Publication number: 20250112034
    Abstract: A wide-size range aerodynamic focusing lens may include a virtual impactor comprising an inlet nozzle, a major flow tube, and a receiving nozzle. A wide-size range aerodynamic focusing lens may include a plurality of grouped focusing elements comprising a first focusing lens element group, a refocusing lens element group, and a second focusing lens element group, and. A wide-size range aerodynamic focusing lens may include an accelerating nozzle. A wide-size range aerodynamic focusing lens may include a plurality of spacers where the diameter ratio of the spacer proximal to a lens element can range from 2 to 20.
    Type: Application
    Filed: October 2, 2024
    Publication date: April 3, 2025
    Inventor: Xiaoling Wang
  • Publication number: 20250067307
    Abstract: A disconnection mechanism, for engaging or disengaging a fixed component and a movable component arranged on a first shaft extending in a first direction. The disconnection mechanism includes a shift fork, connected to the movable component, and constructed to be able to reciprocate linearly in the first direction, so that the movable component is engaged with or disengaged from the fixed component. An actuator includes an output end which rotates about a rotation axis of the actuator at a distance from the rotation axis. A drive rod has a first end rotatably connected to the output end and a second end rotatably connected to the shift fork, so that the output end, when rotating, is able to drive the shift fork to reciprocate linearly.
    Type: Application
    Filed: August 20, 2024
    Publication date: February 27, 2025
    Applicant: VALEO EMBRAYAGES
    Inventors: Yifan GU, Yejin JIN, Xiaoling WANG, Ying HAO, Dongdong WANG, Xucan CHEN
  • Patent number: 12225712
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple initial active pillars on the substrate; forming a gate layer between initial active pillars; and forming a first dielectric layer with openings on the gate layer and on the initial active pillars; removing part of the initial active pillar located in each opening to form an active pillar; and removing part of the gate layer to form an isolation trench and a word line, such that two adjacent active pillars in the same row are located on two sides of the isolation trench.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: February 11, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi Wu, Xiaoling Wang
  • Patent number: 12219752
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base and forming, on the base, a bit line contact region provided with a first groove; forming a first bit line contact layer in the first groove, wherein the first bit line contact layer in the first groove defines a second groove; forming a diffusion layer in the second groove, wherein the diffusion layer in the second groove defines a third groove; forming, in the third groove, a second bit line contact layer provided with a gap; and processing the diffusion layer.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: February 4, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Cheng Chen, Hai-Han Hung, Chun-Chieh Huang, Xiaoling Wang
  • Patent number: 12211767
    Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: January 28, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Luguang Wang, Xiaoling Wang
  • Patent number: 12195367
    Abstract: The present disclosure provides an electrolytic module unit based on a boron-doped diamond (BDD) electrode, including a water flow guide module and an electrolytic module. The electrolytic module is provided within the water flow guide module. The electrolytic module includes a BDD electrode including a main body portion and a plurality of branch portions disposed on two sides of the main body portion. The main body portion and the plurality of branch portions on two sides of the main body portion constitute a fishbone-like structure. The BDD electrode of the electrolytic module unit is of the fishbone-like structure.
    Type: Grant
    Filed: June 5, 2024
    Date of Patent: January 14, 2025
    Assignees: JIANGXI XINYUAN NEW MATERIAL TECHNOLOGY CO., LTD., SINOMA SYNTHETIC CRYSTALS (SHANDONG) CO., LTD., SHANDONG XINYUAN NEW MATERIAL TECHNOLOGY CO., LTD.
    Inventors: Yubao Wang, Xiaobo Zhao, Jinchang Xu, Yanxin Cao, Xiaoling Wang, Xinwei Zhang, Mingzhao Liu, Jingqun Zhang, Peng Zi, Chuanqi Wang, Huayang Wei
  • Patent number: 12131979
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, the base including a substrate and a first heat dissipation structure located in the substrate, heat conductivity of the first heat dissipation structure being higher than that of the substrate, the substrate including an upper surface and a lower surface opposite to each other, and a surface of the first heat dissipation structure being exposed on the upper surface of the substrate; a second heat dissipation structure, the second heat dissipation structure being at least located on an upper surface of the first heat dissipation structure; and a through silicon via (TSV) structure, the TSV structure penetrating through an entire thickness of the second heat dissipation structure and extending into the base, the second heat dissipation structure surrounding the TSV structure, and the first heat dissipation structure surrounding the TSV structure.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: October 29, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Luguang Wang, Xiaoling Wang