Patents by Inventor Xiaomeng Chen
Xiaomeng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8816358Abstract: Some embodiments of the present disclosure relate to an optical sensor. The optical sensor includes a first electrode disposed over a semiconductor substrate. A photoelectrical conversion element, which includes a p-type layer and an n-type layer, is arranged over the first electrode to convert one or more photons having wavelength falling within a predetermined wavelength range into an electrical signal. A second electrode is disposed over the photoelectrical conversion element. The second electrode is transparent in the predetermined wavelength range. A color filter element, which is made up of plasmonic nanostructures, is disposed over the second electrode.Type: GrantFiled: July 3, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shu-Ju Tsai, Yeur-Luen Tu, Cheng-Ta Wu, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
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Patent number: 8802538Abstract: Methods for hybrid wafer bonding. In an embodiment, a method is disclosed that includes forming a metal pad layer in a dielectric layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrates to expose a surface of the metal pad layer and planarize the dielectric layer to form a bonding surface on each semiconductor substrate; performing an oxidation process on the at least two semiconductor substrates to oxidize the metal pad layer to form a metal oxide; performing an etch to remove the metal oxide, recessing the surface of the metal pad layer from the bonding surface of the dielectric layer of each of the at least two semiconductor substrates; physically contacting the bonding surfaces of the at least two semiconductor substrates; and performing a thermal anneal to form bonds between the metal pads of the semiconductor substrates. Additional methods are disclosed.Type: GrantFiled: June 26, 2013Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Yin Liu, Jen-Cheng Liu, Xiaomeng Chen, Xin-Hua Huang, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
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Patent number: 8754446Abstract: The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.Type: GrantFiled: August 30, 2006Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, Shwu-Jen Jeng, Byeong Y. Kim, Hasan M. Nayfeh
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Publication number: 20140117546Abstract: The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ping-Yin LIU, Szu-Ying CHEN, Chen-Jong WANG, Chih-Hui HUANG, Xin-Hua HUANG, Lan-Lin CHAO, Yeur-Luen TU, Chia-Chiung TSAI, Xiaomeng CHEN
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Publication number: 20140064034Abstract: Some implementations provide techniques and arrangements for distance measurements between computing devices. Some examples determine a distance between devices based at least in part on a propagation time of audio tones between the devices. Further, some examples determine the arrival time of the audio tones by performing autocorrelation on streaming data corresponding to recorded sound to determine a timing of an autocorrelation peak indicative of a detection of an audio tone in the streaming data. In some cases, cross correlation may be performed on the streaming data in a search window to determine a timing of a cross correlation peak indicative of the detection of the audio tone in the streaming data. The location of the search window in time may be determined based at least in part on the timing of the detected autocorrelation peak.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Applicant: MICROSOFT CORPORATIONInventors: Zengbin Zhang, David Chiyuan Chu, Thomas Moscibroda, Xiaomeng Chen, Feng Zhao
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Patent number: 8513779Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: GrantFiled: July 27, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Publication number: 20120292668Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: ApplicationFiled: July 27, 2012Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Patent number: 8288281Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.Type: GrantFiled: July 16, 2010Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
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Patent number: 8242544Abstract: A method for reducing resist poisoning is provided. The method includes forming a first structure in a dielectric on a substrate and reducing amine related contaminants from the dielectric and the substrate created after the formation of the first structure. The method further includes forming a second structure in the dielectric. A first organic film may be formed on the substrate which is then heated and removed from the substrate to reduce the contaminant. Alternatively, a plasma treatment or cap may be provided. A second organic film is formed on the substrate and patterned to define a second structure in the dielectric.Type: GrantFiled: December 7, 2004Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
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Patent number: 8237247Abstract: The present invention relates to complementary devices, such as n-FETs and p-FETs, which have hybrid channel orientations and are connected by conductive connectors that are embedded in a semiconductor substrate. Specifically, the semiconductor substrate has at least first and second device regions of different surface crystal orientations (i.e., hybrid orientations). An n-FET is formed at one of the first and second device regions, and a p-FET is formed at the other of the first and second device regions. The n-FET and the p-FET are electrically connected by a conductive connector that is located between the first and second device regions and embedded in the semiconductor substrate. Preferably, a dielectric spacer is first provided between the first and second device regions and recessed to form a gap therebetween. The conductive connector is then formed in the gap above the recessed dielectric spacer.Type: GrantFiled: September 8, 2009Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Yoichi Otani
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Patent number: 8053838Abstract: A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.Type: GrantFiled: June 26, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, Byeong Yeol Kim, Mahender Kumar, Huilong Zhu
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Patent number: 7993990Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: GrantFiled: April 9, 2010Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devendra K. Sadana
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Publication number: 20100279508Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.Type: ApplicationFiled: July 16, 2010Publication date: November 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiaomeng Chen, William Cote, Anthony K. Stamper, Arthur C. Winslow
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Patent number: 7803708Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.Type: GrantFiled: September 29, 2006Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Xiaomeng Chen, William Cote, Anthony K Stamper, Arthur C Winslow
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Patent number: 7790553Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.Type: GrantFiled: July 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Bachir Dirahoui, Jay W. Strane, Gregory G. Freeman
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Patent number: 7790581Abstract: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.Type: GrantFiled: January 9, 2006Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Woo-Hyeong Lee, Huilong Zhu
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Publication number: 20100197118Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: ApplicationFiled: April 9, 2010Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devendra K. Sadana
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Patent number: 7696573Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.Type: GrantFiled: October 31, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Paul David Agnello, Xiaomeng Chen, Judson R. Holt, Mukesh Vijay Khare, Byeong Y. Kim, Devandra K. Sadana
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Publication number: 20100006926Abstract: Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.Type: ApplicationFiled: July 10, 2008Publication date: January 14, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: HUILONG ZHU, Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Bachir Dirahoui, Jay W. Strane, Gregory G. Freeman
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Publication number: 20090321828Abstract: A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.Type: ApplicationFiled: June 26, 2008Publication date: December 31, 2009Applicant: International Business Machines CorporationInventors: Xiaomeng Chen, Byeong Yeol Kim, Mahender Kumar, Huilong Zhu