Patents by Inventor Xiaomeng Chen

Xiaomeng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dual facing BSI image sensors with wafer level stacking
    Patent number: 9711555
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR
    Publication number: 20170133384
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.
    Type: Application
    Filed: January 23, 2017
    Publication date: May 11, 2017
    Inventors: Chern-Yow Hsu, Chen Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Alignment systems and wafer bonding systems and methods
    Patent number: 9646860
    Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Xiaomeng Chen, Ping-Yin Liu, Lan-Lin Chao
  • SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR
    Publication number: 20170077104
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Air Trench in Packages Incorporating Hybrid Bonding
    Publication number: 20170069593
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Application
    Filed: November 21, 2016
    Publication date: March 9, 2017
    Inventors: Bruce C.S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • SEMICONDUCTOR ARRANGEMENT HAVING CAPACITOR SEPARATED FROM ACTIVE REGION
    Publication number: 20170025417
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Application
    Filed: October 10, 2016
    Publication date: January 26, 2017
    Inventors: Chern-Yow Hsu, Cheng-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Semiconductor arrangement with capacitor
    Patent number: 9553096
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai, Xiaomeng Chen, Chen-Jong Wang
  • Method of manufacturing a semiconductor device including a barrier structure
    Patent number: 9548376
    Abstract: A method of manufacturing a semiconductor device includes forming a barrier structure over a substrate. The method further includes forming a channel layer over the barrier structure. The method further includes depositing an active layer over the channel layer. The method further includes forming source/drain electrodes over the channel layer. The method further includes annealing the source/drain electrodes to form ohmic contacts in the active layer under the source/drain electrodes.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 17, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Integrate Rinse Module in Hybrid Bonding Platform
    Publication number: 20170004964
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 5, 2017
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Method and apparatus to protect a wafer edge
    Patent number: 9508659
    Abstract: A method includes holding bonded wafers by a wafer holding module. A gap between the bonded wafers along an edge is filled with a protection material.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Yeur-Luen Tu, Shu-Ju Tsai, Cheng-Ta Wu, Chia-Shiung Tsai, Xiaomeng Chen
  • Semiconductor arrangment with capacitor
    Patent number: 9508722
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai, Xiaomeng Chen, Chen-Jong Wang
  • Air trench in packages incorporating hybrid bonding
    Patent number: 9502396
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Method of manufacturing a semiconductor device
    Patent number: 9478632
    Abstract: A method of making a semiconductor device includes epitaxially growing a channel layer over a substrate. The method further includes depositing an active layer over the channel layer. Additionally, the method includes forming a gate structure over the active layer, the gate structure configured to deplete a 2DEG under the gate structure, the gate structure including a dopant. Furthermore, the method includes forming a barrier layer between the gate structure and the active layer, the barrier layer configured to block diffusion of the dopant from the gate structure into the active layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 25, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Chun Liu, Chi-Ming Chen, Chen-Hao Chiang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Semiconductor arrangement having capacitor separated from active region
    Patent number: 9466663
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai, Xiaomeng Chen, Chen-Jong Wang
  • Transistor having a back-barrier layer and method of making the same
    Patent number: 9455341
    Abstract: A transistor includes a substrate and a buffer layer on the substrate, wherein the buffer layer comprises p-type dopants. The transistor further includes a channel layer on the buffer layer and a back-barrier layer between a first portion of the channel layer and a second portion of the channel layer. The back-barrier layer has a band gap discontinuity with the channel layer. The transistor further includes an active layer on the second portion of the channel layer, wherein the active layer has a band gap discontinuity with the second portion of the channel layer. The transistor further includes a two dimensional electron gas (2-DEG) in the channel layer adjacent an interface between the channel layer and the active layer.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Chih-Wen Hsiung, Po-Chun Liu, Ming-Chang Ching, Chung-Yi Yu, Xiaomeng Chen
  • MULTI-ARM POLYETHYLENE GLYCOL-AZIDO DERIVATIVE
    Publication number: 20160271266
    Abstract: Provided is a multi-arm polyethylene glycol-azido derivative of general formula I , wherein R is a central molecule,which is selected from a polyhydroxy structure, a polyamino structure or a polycarboxyl structure; n is the number of branches or arms, n 3; PEG is the same or different —(CH2CH2O)m—, the average value of m being an integer from 3 to 250; X is a linking group of a azido end group; k is the number of the branches having the azido end group; F is selected from the group consisting of amino, carboxyl, sulfhydryl, ester group, maleic imide group and acrylic group; and Y is a linking group of an end group F.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Inventors: XIAOMENG CHEN, MEINA LIN, XUAN ZHAO
  • ALKYNYL MULTI-ARM POLYETHYLENE GLYCOL DERIVATIVE
    Publication number: 20160271267
    Abstract: The present invention provides an alkynyl multi-arm polyethylene glycol derivative having a structure of a general formula I or general formula X VIII. In the derivative, X1, X2, X3 and X4 are linking groups, F1, F2, F3 and F4 are end groups, the end groups may be the same or may also be different, and are selected from: hydroxy, carboxyl, ester group, amino, alkynyl or the like, at least one of the end groups is alkynyl, and PEG is the same or different —(CH2CH2O)m—, wherein m is an integer ranging from 3 to 250, and 1 is an integer greater than or equal to 1. The multi-arm polyethylene glycol derivatives have stronger application flexibility, and have good application prospect in aspects such as organic synthesis, medicine synthesis and medical instruments.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Inventors: MEINA LIN, XIAOMENG CHEN
  • STEARIC ACID DERIVATIVES AND OLEIC ACID DERIVATIVES OF MULTI-ARM POLYETHYLENE GLYCOL
    Publication number: 20160272762
    Abstract: Disclosed are multi-arm polyethylene glycol derivatives having structure of formula I or formula VI. Compared with straight chain polyethylene glycol, multi-arm polyethylene glycol has a plurality of terminal groups, thus has a plurality of introducing points of functional groups and can support a plurality of reactive terminal groups, thereby enabling multi-arm polyethylene glycol to have more flexibility and wider range of application.
    Type: Application
    Filed: June 1, 2016
    Publication date: September 22, 2016
    Inventors: JUNYE LI, MEINA LIN, XIAOMENG CHEN
  • Integrate rinse module in hybrid bonding platform
    Patent number: 9446467
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Xin-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Air trench in packages incorporating hybrid bonding
    Patent number: 9443796
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Xin-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen