Patents by Inventor Xiaoning Ye
Xiaoning Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088069Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.Type: ApplicationFiled: February 26, 2021Publication date: March 14, 2024Applicant: Intel CorporationInventors: Wenzhi Wang, Xiaoning Ye, Yunhui Chu, Chunfei Ye, James A. McCall
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Publication number: 20240063134Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and an individual conductive segment may have a conductivity that is close to or less than a conductivity of a conductive line of an individual microstrip.Type: ApplicationFiled: February 26, 2021Publication date: February 22, 2024Applicant: Intel CorporationInventors: Xiaoning Ye, Pooya Tadayon, Wenzhi Wang, Srinivasa R. Aravamudhan, Nathan Somnang Tan, Brett Daniel Grossman
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Publication number: 20220311114Abstract: Electronic structures including a dual-stripline with crosstalk cancellation are described. In an example, a printed circuit board (PCB), a package substrate or a semiconductor die includes a dual-stripline structure. The dual-stripline structure includes a first region including a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line. The dual-stripline structure also includes a second region including the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line. The dual-stripline structure also includes a transition region between the first region and the second region. The first bottom line and the second bottom line cross in the transition region.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: Albert SUTONO, Xiaoning YE
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Publication number: 20220270989Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a first microstrip; a first surface dielectric region over the first microstrip, wherein the first surface dielectric region has a first thickness, and the first thickness is nonzero; a second microstrip; and a second surface dielectric region over the second microstrip, wherein the second surface dielectric region has a second thickness, the second thickness is nonzero, and the first thickness is different than the second thickness.Type: ApplicationFiled: February 24, 2021Publication date: August 25, 2022Applicant: Intel CorporationInventors: Albert Sutono, Xiaoning Ye
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Publication number: 20210378099Abstract: An apparatus is described. The apparatus includes a semiconductor chip package loading assembly having a heat sink and a first magnetic material, the first magnetic material to be mechanically coupled to a first side of a printed circuit board that is opposite a second side of the printed circuit board where input/outputs (I/Os) of the semiconductor chip package interface with the printed circuit board. The first magnetic material to be positioned between the printed circuit board and a second magnetic material. The first magnetic material is to be magnetically attracted to the second magnetic material to impede movement of the heat sink.Type: ApplicationFiled: July 20, 2021Publication date: December 2, 2021Inventors: Phil GENG, Timothy Glen HANNA, Xiaoning YE, Sandeep AHUJA, Jacob MCMILLIAN, Ralph V. MIELE, David SHIA, Jeffory L. SMALLEY
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Patent number: 11169194Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.Type: GrantFiled: February 24, 2020Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Xiaoning Ye, Kai Xiao
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Publication number: 20210311120Abstract: An apparatus may comprise a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal; and a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Jong-Ru Guo, Jingbo Li, Xiaoning Ye, Zuoguo Wu, Howard L. Heck
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Patent number: 10965047Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.Type: GrantFiled: June 4, 2019Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
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Patent number: 10925152Abstract: Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.Type: GrantFiled: September 28, 2018Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Albert Sutono, Xiaoning Ye, Jimmy Hsu, Daniel Hull
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Patent number: 10827627Abstract: A printed circuit board, according one embodiment, includes a reference layer; a dielectric layer disposed on the reference layer; and a conductor layer adhered to the dielectric layer with an adhesive layer disposed between the dielectric layer and the conductor layer. The conductor layer has a smooth surface facing the dielectric layer having a roughness (Rz) of less than two microns.Type: GrantFiled: March 21, 2019Date of Patent: November 3, 2020Assignee: Intel CorporationInventors: Xiaoning Ye, Jimmy Hsu
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Publication number: 20200292603Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.Type: ApplicationFiled: February 24, 2020Publication date: September 17, 2020Inventors: Xiaoning Ye, Kai Xiao
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Patent number: 10571501Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.Type: GrantFiled: March 15, 2017Date of Patent: February 25, 2020Assignee: Intel CorporationInventors: Xiaoning Ye, Kai Xiao
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Publication number: 20190288421Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Applicant: Intel CorporationInventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
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Publication number: 20190223299Abstract: A printed circuit board, according one embodiment, includes a reference layer; a dielectric layer disposed on the reference layer; and a conductor layer adhered to the dielectric layer with an adhesive layer disposed between the dielectric layer and the conductor layer. The conductor layer has a smooth surface facing the dielectric layer having a roughness (Rz) of less than two microns.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Inventors: Xiaoning Ye, Jimmy Hsu
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Publication number: 20190045623Abstract: Apparatuses, systems and methods associated with dielectric coatings for printed circuit boards are disclosed herein. In embodiments, a printed circuit board (PCB) includes a substrate, microstrip conductors located on a surface of the substrate, a solder mask covering the surface of the substrate and the microstrip conductors, and a dielectric coating located on the solder mask, the dielectric coating on an opposite side of the solder mask from the microstrip conductors, wherein a thickness of the dielectric coating is selected to cause a ratio of capacitive coupling to self capacitance to be approximately equal to a ratio of inductive coupling to self inductance for each microstrip conductor of the microstrip conductors, where the thickness may be determined based on a specific methodology including simulations. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 28, 2018Publication date: February 7, 2019Inventors: Albert Sutono, Xiaoning Ye, Jimmy Hsu, Daniel Hull
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Patent number: 9893761Abstract: Generally, this disclosure provides systems and devices for reduction of crosstalk between routed signals. A system may include a first pair of signal lines and a second pair of signal lines and each of the pairs of signal lines include a positive signal line and a negative signal line to transmit a differential signal. The system may also include an alternating current coupling capacitor (AC cap) associated with each of the positive signal lines and each of the negative signal lines. The system may further include a routing crossover of the positive signal line and the negative signal line of the second pair of signal lines, to decrease signal crosstalk between the first and second pairs of signal lines. The routing crossover may include at least one of the AC caps.Type: GrantFiled: September 25, 2014Date of Patent: February 13, 2018Assignee: INTEL CORPORATIONInventors: Xiaoning Ye, Yunhui Chu, Zhenwei Yu
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Publication number: 20170269136Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.Type: ApplicationFiled: March 15, 2017Publication date: September 21, 2017Inventors: Xiaoning Ye, Kai Xiao
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Patent number: 9750129Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 14, 2016Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
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Patent number: 9554454Abstract: Generally discussed herein are systems, apparatuses, and methods that relate to reducing crosstalk in a differential signal pair. According to an example, a device may include a first pair of differential signal lines comprising a first signal line and a second signal line proximate the first signal line, the first signal line and the second signal line separated from each other along a first line, and a second pair of differential signal lines comprising a third signal line proximate a fourth signal, the third signal line and the fourth signal separated from each other along a second line generally perpendicular to the first line.Type: GrantFiled: December 17, 2014Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Chong Richard Zhao, Xiaoning Ye
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Publication number: 20170006698Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye