Patents by Inventor Xiaoning Ye

Xiaoning Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9485854
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
  • Publication number: 20160181682
    Abstract: Generally discussed herein are systems, apparatuses, and methods that relate to reducing crosstalk in a differential signal pair. According to an example, a device may include a first pair of differential signal lines comprising a first signal line and a second signal line proximate the first signal line, the first signal line and the second signal line separated from each other along a first line, and a second pair of differential signal lines comprising a third signal line proximate a fourth signal, the third signal line and the fourth signal separated from each other along a second line generally perpendicular to the first line.
    Type: Application
    Filed: December 17, 2014
    Publication date: June 23, 2016
    Inventors: Chong Richard Zhao, Xiaoning Ye
  • Publication number: 20160094272
    Abstract: Generally, this disclosure provides systems and devices for reduction of crosstalk between routed signals. A system may include a first pair of signal lines and a second pair of signal lines and each of the pairs of signal lines include a positive signal line and a negative signal line to transmit a differential signal. The system may also include an alternating current coupling capacitor (AC cap) associated with each of the positive signal lines and each of the negative signal lines. The system may further include a routing crossover of the positive signal line and the negative signal line of the second pair of signal lines, to decrease signal crosstalk between the first and second pairs of signal lines. The routing crossover may include at least one of the AC caps.
    Type: Application
    Filed: September 25, 2014
    Publication date: March 31, 2016
    Applicant: Intel Corporation
    Inventors: XIAONING YE, YUNHUI CHU, ZHENWEI YU
  • Patent number: 9293798
    Abstract: Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventor: Xiaoning Ye
  • Publication number: 20160057851
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Shaowu Huang, Kai Xiao, Beom-Taek Lee, Boping Wu, Xiaoning Ye
  • Patent number: 9113555
    Abstract: A method of reducing crosstalk. The method may include forming a first contact over a first vertical conductor. The method may include forming a second contact over a second vertical conductor. The method may include forming a capacitive coupler between the first contact and the second contact, wherein the capacitive coupler is to cancel crosstalk received at the second vertical conductor from the first vertical conductor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 18, 2015
    Assignee: Intel Corporation
    Inventors: Raul Enriquez Shibayama, Xiaoning Ye, Kai Xiao, Benjamin Lopez Garcia
  • Publication number: 20140179162
    Abstract: A method of reducing crosstalk. The method may include forming a first contact over a first vertical conductor. The method may include forming a second contact over a second vertical conductor. The method may include forming a capacitive coupler between the first contact and the second contact, wherein the capacitive coupler is to cancel crosstalk received at the second vertical conductor from the first vertical conductor.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Raul Enriquez Shibayama, Xiaoning Ye, Kai Xiao, Benjamin Lopez Garcia
  • Publication number: 20140091873
    Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 3, 2014
    Inventor: Xiaoning Ye
  • Patent number: 8624687
    Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventor: Xiaoning Ye
  • Publication number: 20130278348
    Abstract: Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 24, 2013
    Inventor: Xiaoning Ye
  • Publication number: 20120161893
    Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventor: Xiaoning Ye
  • Publication number: 20120160542
    Abstract: In some embodiments a plurality of differential pair traces include microstrip routing and a layer is formed over the plurality of differential pair traces. The layer formed over the plurality of differential pair traces is a thick solder mask, a dielectric layer, and/or a solder mask with a high dielectric constant. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Olufemi B. Oluwafemi, Xiaoning Ye
  • Patent number: 7965763
    Abstract: In one embodiment, the present invention includes a method for receiving a jitter profile and a step response of a channel coupled between a transmitter and a receiver and a bit pattern to be transmitted, transmitting the bit pattern along the channel from the transmitter to the receiver with the jitter profile and the step response, receiving the bit pattern at the receiver and converting the bit pattern to a data stream by interpolating the step response according to a jitter of a current bit to obtain a jittery step response, superposing the jittery step response onto the data stream, calculating the jitter at each transition bit of the bit pattern by determining a time difference between actual and ideal crossing points, incrementing a jitter distribution function with the jitter, and generating a timing curve for the channel using the jitter distribution function. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventors: Kai Xiao, Beomtaek Lee, Xiaoning Ye, Chung-Chi Huang
  • Patent number: 7573359
    Abstract: An electronic device may be formed of a printed circuit board having integrated circuits mounted thereon. A backing plate may compress an insulating layer against a microstrip line formed on one surface of said circuit board opposite to the surface that includes integrated circuits. By compressing said backing plate against said insulating layer, less crosstalk may result from the formation of a microstrip on the bottom surface of the printed circuit board. The backing plate may also be used to secure a cooling device, such as a heat sink, on the opposite side of the circuit board.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: August 11, 2009
    Assignee: Intel Corporation
    Inventors: Richard K. Kunze, Olufemi B. Oluwafemi, Chung-Chi Huang, Xiaoning Ye
  • Publication number: 20090110042
    Abstract: In one embodiment, the present invention includes a method for receiving a jitter profile and a step response of a channel coupled between a transmitter and a receiver and a bit pattern to be transmitted, transmitting the bit pattern along the channel from the transmitter to the receiver with the jitter profile and the step response, receiving the bit pattern at the receiver and converting the bit pattern to a data stream by interpolating the step response according to a jitter of a current bit to obtain a jittery step response, superposing the jittery step response onto the data stream, calculating the jitter at each transition bit of the bit pattern by determining a time difference between actual and ideal crossing points, incrementing a jitter distribution function with the jitter, and generating a timing curve for the channel using the jitter distribution function. Other embodiments are described and claimed.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: Kai Xiao, Beomtaek Lee, Xiaoning Ye, Chung-Chi Huang
  • Publication number: 20080314620
    Abstract: According to embodiments, small holes or openings may be cut on or through the ground plane(s) adjacent to a selected trace line, so that C and L will be changed accordingly. Then phase velocity will also be changed. As a result, the flying time from one location or point to a different location or point of the transmission line will also be changed. This concept applies to a single trace. Similarly, this concept may be applied to one trace of a differential pair of traces (e.g., so that the two parts of the differential signal transmitted at one point in time at a location on the pair arrive at the same time at another location of the pair).
    Type: Application
    Filed: August 19, 2008
    Publication date: December 25, 2008
    Inventors: Chunfei Ye, Xiaoning Ye
  • Patent number: 7450396
    Abstract: According to embodiments, small holes or openings may be cut on or through the ground plane(s) adjacent to a selected trace line, so that C and L will be changed accordingly. Then phase velocity will also be changed. As a result, the flying time from one location or point to a different location or point of the transmission line will also be changed. This concept applies to a single trace. Similarly, this concept may be applied to one trace of a differential pair of traces (e.g., so that the two parts of the differential signal transmitted at one point in time at a location on the pair arrive at the same time at another location of the pair).
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Chunfei Ye, Xiaoning Ye
  • Publication number: 20080238584
    Abstract: An electronic device may be formed of a printed circuit board having integrated circuits mounted thereon. A backing plate may compress an insulating layer against a microstrip line formed on one surface of said circuit board opposite to the surface that includes integrated circuits. By compressing said backing plate against said insulating layer, less crosstalk may result from the formation of a microstrip on the bottom surface of the printed circuit board. The backing plate may also be used to secure a cooling device, such as a heat sink, on the opposite side of the circuit board.
    Type: Application
    Filed: March 29, 2007
    Publication date: October 2, 2008
    Inventors: Richard K. Kunze, Olufemi B. Oluwafemi, Chung-Chi Huang, Xiaoning Ye
  • Patent number: 7361994
    Abstract: A system may include a conductive plane defining a non-conductive antipad area and a second non-conductive area extending from the antipad area in at least a first direction, a dielectric plane coupled to the conductive plane, a conductive via passing through the dielectric plane and the antipad area, a conductive pad connected to an end of the conductive via, and a conductive trace coupled to the dielectric plane and connected to the conductive pad, the conductive trace extending from the conductive pad in the first direction.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventor: Xiaoning Ye
  • Publication number: 20080080155
    Abstract: According to embodiments, small holes or openings may be cut on or through the ground plane(s) adjacent to a selected trace line, so that C and L will be changed accordingly. Then phase velocity will also be changed. As a result, the flying time from one location or point to a different location or point of the transmission line will also be changed. This concept applies to a single trace. Similarly, this concept may be applied to one trace of a differential pair of traces (e.g., so that the two parts of the differential signal transmitted at one point in time at a location on the pair arrive at the same time at another location of the pair).
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventors: Chunfei Ye, Xiaoning Ye