METHOD AND SYSTEM FOR PHYSICAL-LAYER HANDSHAKING FOR TIMING ROLE TRANSITION

Abstract

Aspects of a method and system for physical-layer handshaking for timing role transition are provided. Prior to changing the timing role of a first Ethernet device, the first Ethernet device may communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more PCS code-groups. In response to a determination to change the timing role of the first Ethernet device, the first Ethernet device may communicate one or more IDLE symbols over the Ethernet link to the second Ethernet device. The IDLE symbol(s) may be generated utilizing a second set of one or more PCS code-groups. The first set of PCS code-group(s) may be mutually exclusive with the second set of PCS code-group(s). In response to detecting a received Ethernet physical layer symbol corresponding to the second set of PCS code-groups, the second Ethernet device may make a determination to change its timing role.

Description

CLAIM OF PRIORITY

This patent application makes reference to, claims priority to and claims benefit from U.S. Provisional Patent Application Ser. No. 61/388,106 filed on Sep. 30, 2010 and U.S. Provisional Patent Application Ser. No. 61/353,261 filed on Jun. 20, 2010.

Each of the above stated applications is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

Certain embodiments of the invention relate to networking. More specifically, certain embodiments of the invention relate to a method and system for physical-layer handshaking for timing role transition.

BACKGROUND OF THE INVENTION

Packet based communications networks, such as Ethernet, are becoming an increasingly popular means of communicating data of various types and sizes for a variety of applications. Another area of concern in modern packet based networks is the ability to support various functions that require accurate timing. In this regard, packet based networks are increasingly being utilized to carry traffic such as voice, and multimedia traffic that require accurate timing so as not to degrade user experience. However, conventional timing methods have many shortcomings.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for physical-layer handshaking for timing role transition, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other advantages, aspects and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are block diagrams illustrating a pair of network devices operable to switch which device operates as timing master independent of which device operates as IEEE 802.3 master, in accordance with an embodiment of the invention.

FIGS. 2A-2C illustrates a transition from timing slave to timing master, in accordance with an embodiment of the invention.

FIGS. 3A-3C illustrates a transition from timing master to timing slave, in accordance with an embodiment of the invention.

FIG. 4 is a flowchart illustrating exemplary steps for managing timing master and timing slave configuration for an Ethernet link, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a method and system for physical-layer handshaking for timing role transition. In various embodiments of the invention, prior to changing the timing role of a first Ethernet device, the first Ethernet device may communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more physical coding sublayer (PCS) code-groups. In response to a determination to change the timing role of the first Ethernet device, the first Ethernet device may communicate one or more IDLE symbols over the Ethernet link to the second Ethernet device, where the one or more IDLE symbol may be generated utilizing a second set of one or more PCS code-groups. The first set of one or more PCS code-groups may be mutually exclusive with the second set of one or more PCS code-groups. The timing role of the first Ethernet device may be changed from timing slave to timing master. An Ethernet physical layer connection between the first Ethernet device and the second Ethernet device may remain active during the changing of the first Ethernet device's timing role. Upon completion of the changing of the timing role from timing slave to timing master, the first Ethernet device may resume communication over the Ethernet link utilizing the first set of one or more PCS code-groups. The determination to change the timing role of the first Ethernet device may be made in response to Ethernet Synchronization Message Channel (ESMC) messages communicated to the first Ethernet device.

In various embodiments of the invention, an Ethernet device may receive Ethernet physical layer symbols via an Ethernet physical layer connection. In response to detecting that one or more of the Ethernet physical layer symbols correspond to a particular set of one or more physical coding sublayer (PCS) code-groups, the Ethernet device may make a determination to change its timing role. The Ethernet device may change its timing role from timing master to timing slave. An Ethernet physical layer connection between the Ethernet device and a second Ethernet device may remain active during the changing of the timing role. The Ethernet device may remain IEEE 802.3 master before, during, and after the changing of its timing role.

FIGS. 1A and 1B are block diagrams illustrating a pair of network devices operable to switch which device operates as timing master independent of which device operates as IEEE 802.3 master, in accordance with an embodiment of the invention. Referring to FIGS. 1A and 1B, there is shown network devices 102A and 102B between which there is an active Ethernet physical layer (or similar) connection via link 110, where “active” means that communications may commence or continue without having to undergo autonegotiation or other similar connection-establishment routine. Also shown is a timing source 104A, Ethernet PHYs 106A₁ and 106A₂, a timing source 104B, and Ethernet PHYs 106B₁ and 106B₂.

Each of the PHYs 106A₁, 106A₂, 106B₁, and 106B₂ may comprise suitable logic, circuitry, interfaces, and/or code that may enable communications in accordance with one or more Ethernet physical layer protocols such as, for example, 10BASE-X, 100BASE-X, 1GBASE-X, 10GBASE-X, 40GBASE-X, and 100GBASE-X, where ‘X’ is a refers to any of the various physical media types set forth in the IEEE 802.3 standard. Each of the PHYs 106A₁, 106A₂, 106B₁, and 106B₂ may comprise a PLL 108, or other clock generator, that may be utilized for transmission and reception of data. For synchronous Ethernet communications, the PLL 108 may be phase and/or frequency locked to the clock signal 105.

The timing source 104A may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to perform various functions for supporting synchronous Ethernet communications. Exemplary functions may comprise clock generation and synchronization. The timing source 104A may generate a clock 105A which may be provided to the PHYs 106A₁ and 106A₂. The timing source 104A may be operable to synchronize the phase and/or frequency of the clock 105 to a selected reference clock. The selected reference clock may be dynamically selected from a plurality of available reference clocks. The selected reference clock may be selected in a manner that is transparent to the PHYs 106A₁ and 106A₂. For example, for PHYs 106A₁ and 106A₂ configured to communicate compliant with 100/1G/10GBASE-T, a change in selected reference clock may be done without the PHYs 106A₁ and 106A₂ losing their active physical Ethernet layer connection (“losing link-up”) with their respective link partners and having to re-enter autonegotiation. To synchronize clock 105 to a first reference clock, PRC, the timing source 104A may utilize synchronization information received via the PHY 106A₁. To synchronize clock 105 to a second reference clock, PRC′, the timing source 104A may utilize synchronization information received via the PHY 106A₁. The timing source 104A may be operable to output an indication of the selected reference clock to the PHYs 106A₁ and 106A₂. The timing source 104B may be substantially similar to the timing source 104A.

In operation of an exemplary embodiment of the invention, referring to FIG. 1A, the PHYs 106A₁ and 106B₂ may be connected via the link 110 and may enter autonegotiation, or an equivalent procedure, to configure speed, duplex mode, and master/slave configuration. For purposes of illustration, it is assumed that the PHY 106A₁ is configured to be the IEEE 802.3 master and PHY 106B₂ is configured to be the IEEE 802.3 slave. A timing master may also be assigned during autonegotiation or shortly thereafter. In various embodiments of the invention, the initial timing master may be selected, for example, to be the IEEE 802.3 master, to be the IEEE 802.3 slave, or may be selected randomly or based on some other parameter such as a network address. For purposes of illustration, it may be assumed that the PHYs 106A₂ and 106B₁ have active Ethernet physical layer connections to their respective link partners (not shown) via links 112A and 112B, respectively.

After a Ethernet physical layer connection is established between PHYs 106A₁ and 106B₂, normal data and/or IDLE symbols generated utilizing a first encoding corresponding to a first set of one or more PCS code-groups may be communicated over the link 110. These communications may include Ethernet Synchronization Message Channel (ESMC) messages, which may similarly be communicated over the link 112A and the link 112B. The timing sources 104A and 104B may each utilize the ESMC messages in selecting a reference clock to which the clocks 105A and 105B, respectively, are synchronized.

In FIG. 1A, the reference clock PRC, which reaches the network device 102B via the PHY 106B₁, is the selected reference clock. Consequently, for the connection between the network device 102A and 102B, the network device 102B is configured as timing master and the network device 102A is configured as the timing slave. Timing source 104A indicates network device 102A′s designation as timing slave to the PHY 106A₁ via the signal 114A. Similarly, timing source 104B indicates network device 102B's designation as timing slave to the PHY 106A₁ via the signal 114A.

In FIG. 18, the reference clock PRC′, which reaches the network device 102A via the PHY 106A₂, is the selected reference clock. Consequently, for the connection between the network device 102A and 102B, the network device 102A is configured as timing master and the network device 102B is configured as the timing slave. Timing source 104A indicates network device 102A's designation as timing master to the PHY 106A₁ via the signal 114A. Similarly, timing source 104B indicates network device 102B's designation as timing master to the PHY 106A₁ via the signal 114A. In FIG. 1B, the network device 102A remains IEEE 802.3 slave and network device 102B remains IEEE 802.3 master, despite the switched timing roles.

Aspects of the invention enable transitioning from the configuration depicted in FIG. 1A to the configuration depicted in FIG. 1B, without tearing down the Ethernet physical layer connection between network devices 102A and 102B. Exemplary details of such a transition are further described below.

FIGS. 2A-2C illustrates a transition from timing slave to timing master, in accordance with an embodiment of the invention. Referring to FIGS. 2A-2C, there is shown the PHY device 106A₁ comprising control module 202, memory 204, physical coding sublayer (PCS) 206, and physical medium attachment sublayer (PMA) 208.

The control module 202 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to configure and/or control operations of various portions of the PHY 106A₁. The control module 202 may, for example, execute instructions stored in the memory 204 and/or implement a state machine.

The memory 204 may comprise, for example, RAM, ROM, flash and/or any other suitable memory elements. The memory 204 may, for example, comprise state registers utilized by the control module 202 and/or may store instruction executed by the control module 202. In an embodiment of the invention, the memory 204 may be utilized to buffer Tx data input to the PHY 106A₁ from a media access control (MAC) layer and/or to buffer Rx data received via the PMA sublayer 208 and PCS sublayer 206.

The PCS 206 may comprise suitable logic, circuitry, interfaces, and/or code operable to convert Tx data from the MAC layer to PCS code-groups. For example, for 1GBASE-T, eight data bits are converted four quinary symbols. In an embodiment of the invention, the PCS 206 may utilize a first encoding corresponding to a first set of code-groups when signal 220 is in a first state and may utilize a second encoding corresponding to a second set of code-groups when the signal 220 is in a second state. The first set of code-groups and the second set of code-groups may be mutually exclusive. In an embodiment of the invention, the first set of code-groups may be the code-groups defined in the IEEE 802.3-2008 as of the filing date of this application.

In an exemplary embodiment of the invention, for 1000BASE-T, the two encodings may be achieved by replacing the equations for cext_n and cexterr_n in § 40.3.1.3.4 of the IEEE 802.3 standard with the following

${\mathrm{cext}}_n=[\begin{array}{cc}\mathrm{tx\_}{\mathrm{error}}_n& \mathrm{if}((\begin{array}{c}\left(\mathrm{tx\_}{\mathrm{enable}}_n=0\right)\mathrm{and}\\ \left(\begin{array}{c}\left({\mathrm{TXD}}_n\left[7\text{:}0\right]=0\times 0F\right)\mathrm{or}\\ \left(\mathrm{loc\_syncE}\mathrm{\_switch}=\mathrm{true}\right)\end{array}\right)\end{array}\\ 0& \mathrm{else}\end{array}\mathrm{cext\_}{\mathrm{err}}_n=[\begin{array}{cc}\mathrm{tx\_}{\mathrm{error}}_n& \mathrm{if}(\begin{array}{c}\left(\begin{array}{c}\left(\mathrm{tx\_}{\mathrm{enable}}_n=0\right)\mathrm{and}\\ \left({\mathrm{TXD}}_n\left[7\text{:}0\right]\ne 0\times 0F\right)\end{array}\right)\mathrm{or}\\ \left(\mathrm{loc\_syncE}\mathrm{\_switch}=\mathrm{true}\right)\end{array})\\ 0& \mathrm{else}\end{array}$

where, for example, loc_syncE_switch corresponds to the signal 220 of FIGS. 2A-2C. That is, while loc_syncE_switch has one value, a first encoding may be used, and when loc_syncC_switch has another value, the second encoding may be used. In other embodiments of the invention, other ways of achieving two mutually exclusive sets of code-groups may be utilized.

The PMA 208 may comprise suitable logic, circuitry, interfaces, and/or code operable to convert the symbols output by the PCS 206 into physical layer signals for transmission, and to convert received physical layer signal into code-groups for conveyance to the PCS 206.

In operation of an exemplary embodiment of the invention, prior to time t₀ the PHY 106A₁ may communicate synchronously with PHY 106B₂ over the link 110 in the role of timing slave. During this time, the PCS 206 may use a first set of code-groups for encoding Tx data and recovering Rx data from received code-groups. The data exchanged may include ESMC messages. During this time the clock 105 may synchronized to PRC received via the network device 102B. Based on the ESMC messages, however, the timing source 104A may determine that PRC is more accurate or otherwise preferable. Accordingly, referring to FIG. 2A, at time t₀ the timing source may trigger the PHY 106A₁ to transition from timing slave to timing master. In an exemplary embodiment of the invention, this may be accomplished by asserting the signal 114. The control module 202 may detect the assertion of signal 114 and may begin reconfiguring various portions of the PHY 106A₁.

Referring to FIG. 2B, there is shown the PHY 106A₁ at time t1, a time instant during 106A₁'s transition from timing slave to timing master. During the transition from timing slave to timing master, the PHY 106A₁ may be configured such that data into the PHY 106A₁ may buffered in the memory 204. During the transition from timing slave to timing master, the PCS 206 may be configured to transmit IDLE symbols utilizing the second encoding corresponding to the second set of code-groups. Such IDLE signals will inform the network device 102B of the timing reconfiguration such that the timing source 104B may trigger reconfiguration of the PHY 106B₂ from timing master to timing slave, as described below in FIGS. 3A-3C.

Referring to FIGS. 2C, there is shown the PHY 106A₁ at time t4, a time instant after which PHYs 106A₁ and 106B₂ have completed transitioning to their new timing roles and communications on the link 110 may resume. Data that was buffered in memory 204 during the transition may be processed for transmission and/or reception. New data arriving at the PHY 106A₁ may be processed for transmission and/or reception rather than being buffered in the memory 204. The PCS 206 may resume using the first encoding corresponding to the first set of code-groups.

FIGS. 3A-3C illustrates a transition from timing master to timing slave, in accordance with an embodiment of the invention. Referring to FIGS. 3A-3C, there is shown the PHY device 106B₂ comprising control module 302, memory 304, physical coding sublayer (PCS) 306, and physical medium attachment sublayer (PMA) 308.

The control module 302, the memory 304, the PCS 306, and the PMA 308 may be substantially similar to, respectively, the control module 202, the memory 204, the PCS 206, and the PMA 208 described with respect to FIGS. 2A-2C.

In operation of an exemplary embodiment of the invention, prior to time t₂ the PHY 1068₂ may communicate synchronously over the link 110 in the role of timing master. At time t₁, however, a code-group from the second set of one or more code-groups may be received and detected by the PHY 106B₂. Receipt of such a code-group may trigger the PHY 106B₂ to transition to the role of timing slave. In an exemplary embodiment of the invention, this may be accomplished by asserting a signal 308 to the control module 302. The control module 302 may detect the assertion of signal 302 and may begin reconfiguring various portions of the PHY 106B₂.

Referring to FIG. 3B, there is shown the PHY 106B₂ at time t3, a time instant during 106B₂'s transition from timing master to timing slave. During the transition from timing master to timing slave, the PHY 106B₂ may be configured such that data into the PHY 106B₂ may buffered in the memory 304.

Referring to FIG. 3C, there is shown the PHY 106B₂ at time t4, a time instant after which PHYs 106A₁ and 106B₂ have completed transitioning to their new timing roles and communications on the link 110 may resume. Data that was buffered in memory 304 during the transition may be processed for transmission and/or reception. New data arriving at the PHY 106B₂ may no longer be buffered in the memory 304 but, rather, be processed for transmission and/or reception rather than being buffered in memory 304.

FIG. 4 is a flowchart illustrating exemplary steps for managing timing master and timing slave configuration for an Ethernet link, in accordance with an embodiment of the invention. Referring to FIG. 4, the exemplary steps may begin with step 402 in which an Ethernet physical layer connection may be established between PHYs 106A₁ and 106B₂. For example, step 402 may comprise autonegotiation. During connection establishment it may be decided which one of the PHYs 106A₁ and 106B₂ will be configured as IEEE 802.3 master and which one will be configured as IEEE 802.3 slave. In an embodiment of the invention, it may be separately determined, during connection establishment, which one of the PHYs 106A₁ and 106B₂ will be configured as timing master for synchronous communications and which one will be configured as timing slave. In an embodiment of the invention, the PHY selected as IEEE 802.3 master may be the default initial timing master. For illustration, it is assumed the PHY 106B₂ is initially the timing master.

In step 404, communications may begin over the established connection. The communications over the Ethernet physical layer connection between devices 102A and 102B may include ESMC messages. Similarly, the device 102A may communicate with another link partner via link 112A and the device 102B may communicate with another link partner via a link 112b. For the communications during this time, the PCS 206 may utilize a first encoding corresponding to a first set of PCS code-groups. The timing source 104B may synchronize to PRC and the device 102B may send ESMC messages to the device 102A to enable the timing source 104A to synchronize to PRC.

In step 406, ESMC messages may continue to be communicated between the devices 102A and 102B and their respective link partners. In step 408, based on the ESMC messages, or based on some other parameter or indication such as request by a network administrator, the network device 102A may determine that the timing roles should be reversed. Accordingly, the PHY 106A₁ may begin transitioning to the role of timing master, while remaining in the role of IEEE 802.3 slave. During this transition, the PHY 106A₁ may buffer traffic input to it.

In step 410, the network device 102A may trigger the PHY 106A₁ to transition to timing master. In step 412, the PHY 106A₁ may send a command to the PHY 106B₂ to trigger the PHY 106B₂ to transition from timing master to timing slave. In an embodiment of the invention, this command may be in the form of one or more IDLE symbols generated utilizing a second PCS encoding corresponding to a second set of one or more PCS code-groups.

In step 414, the PHY 106B₂ may receive the IDLE symbols and detect that the one or more IDLE symbols correspond to a code-group from the second set of one or more code-groups. Accordingly, the PHY 106B₂ may begin transitioning to the role of timing slave. During the transition, the PHY 106B₂ may buffer data input to it.

In step 416, after completing the timing role reversal, both PHYs 106A₁ and 106B₂ may resume communications on the link 110. The PHY 106A₁ may resume utilizing the first PCS encoding corresponding to the first set of PCS code-groups.

Aspects of a method and system for physical-layer handshaking for timing role transition are provided. In an embodiment of the invention, prior to changing the timing role of a first Ethernet device 102A₁, the first Ethernet device 102A₁ may communicate over an Ethernet link 110 to a second Ethernet PHY 1028₂ utilizing a first set of one or more physical coding sublayer (PCS) code-groups. In response to a determination to change the timing role of the first Ethernet device 102A₁, the first Ethernet device 102A₁ may communicate one or more IDLE symbols over the Ethernet link 110 to the second Ethernet device 102B₂, where the one or more IDLE symbol may be generated utilizing a second set of one or more PCS code-groups. The first set of one or more PCS code-groups may be mutually exclusive with the second set of one or more PCS code-groups. The timing role of the first Ethernet device 102A₁ may be changed from timing slave to timing master. An Ethernet physical layer connection between the first Ethernet device 102A₁ and the second Ethernet device 102B₂ may remain active during the changing of the first Ethernet device's timing role. Upon completion of the changing of the timing role from timing slave to timing master, the first Ethernet device 102A₁ may resume communication over the Ethernet link 110 utilizing the first set of one or more PCS code-groups. The determination to change the timing role of the first Ethernet device 102A₁ may be made in response to Ethernet Synchronization Message Channel (ESMC) messages communicated to the first Ethernet device.

In an exemplary embodiment of the invention, an Ethernet device 102B₂ may receive Ethernet physical layer symbols via an Ethernet physical layer connection. In response to detecting that one or more of the Ethernet physical layer symbols correspond to a particular set of one or more physical coding sublayer (PCS) code-groups, the Ethernet device 102B₂ may make a determination to change its timing role. The Ethernet device 102B₂ may change its timing role from timing master to timing slave. An Ethernet physical layer connection between the Ethernet device 102B₂ and a second Ethernet device 102A₁ may remain active during the changing of the timing role. The Ethernet device may remain IEEE 802.3 master before, during, and after the changing of its timing role.

Other embodiments of the invention may provide a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein for physical-layer handshaking for timing role transition.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A method comprising:

prior to changing the timing role of a first Ethernet device, communicating over an Ethernet link to a second Ethernet device utilizing a first set of one or more physical coding sublayer (PCS) code-groups; and

in response to a determination to change the timing role of said first Ethernet device, communicating one or more IDLE symbols over said Ethernet link to said second Ethernet device, wherein said one or more IDLE symbol are generated utilizing a second set of one or more PCS code-groups.

2. The method according to claim 1, wherein said first set of one or more PCS code-groups is mutually exclusive with said second set of one or more PCS code-groups.

3. The method according to claim 1, comprising changing said timing role of said first Ethernet device from timing slave to timing master.

4. The method according to claim 3, wherein an Ethernet physical layer connection between said first Ethernet device and said second Ethernet device remains active during said changing of said timing role.

5. The method according to claim 3, comprising upon completion of said changing said timing role from timing slave to timing master, resuming communication over said Ethernet link utilizing said first set of one or more PCS code-groups.

6. The method according to claim 1, comprising making said determination to change the timing role of said first Ethernet device in response to Ethernet Synchronization Message Channel (ESMC) messages communicated to said first Ethernet device.

7. A method comprising:

in an Ethernet device: receiving Ethernet physical layer symbols via an Ethernet physical layer;

and in response to detecting that one or more of said Ethernet physical layer symbols correspond to a particular set of one or more physical coding sublayer (PCS) code-groups, making a determination to change a timing role of said Ethernet device.

8. The method according to claim 7, comprising changing said timing role of said Ethernet device from timing master to timing slave.

9. The method according to claim 8, wherein an Ethernet physical layer connection between said Ethernet device and a second Ethernet device remains active during said changing of said timing role.

10. The method according to claim 8, wherein said Ethernet device remains IEEE 802.3 master before, during, and after said changing said timing role.

11. A system comprising:

one or more circuits for use in a first Ethernet device, said one or more circuits being operable to: prior to changing the timing role of said first Ethernet device, communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more physical coding sublayer (PCS) code-groups; and in response to a determination to change the timing role of said Ethernet device, communicate one or more IDLE symbols over said Ethernet link to said second Ethernet PHY, wherein said one or more IDLE symbol are generated utilizing a second set of one or more PCS code-groups.

12. The system according to claim 11, wherein said first set of one or more PCS code-groups is mutually exclusive with said second set of one or more PCS code-groups.

13. The system according to claim 11, wherein said one or more circuits are operable to change said timing role of said first Ethernet device from timing slave to timing master.

14. The system according to claim 13, wherein an Ethernet physical layer connection between said first Ethernet device and said second Ethernet device remains active during said changing of said timing role.

15. The system according to claim 13, wherein said one or more circuits are operable to, upon completion said changing said timing role from timing slave to timing master, resume communication over said Ethernet link utilizing said first set of one or more PCS code-groups.

16. The system according to claim 11, wherein said one or more circuits are operable to make said determination to change the timing role of said first Ethernet device in response to Ethernet Synchronization Message Channel (ESMC) messages communicated to said first Ethernet device.

17. A system comprising:

one or more circuits for use in an Ethernet device, said one or more circuits being operable to: receive Ethernet physical layer symbols via an Ethernet physical layer;

and in response to detecting that one or more of said Ethernet physical layer symbols correspond to a particular set of one or more physical coding sublayer (PCS) code-groups, make a determination to change a timing role of said Ethernet device.

18. The system according to claim 17, wherein said one or more circuits are operable to change said timing role of said first Ethernet device from timing master to timing slave.

19. The system according to claim 18, wherein an Ethernet physical layer connection between said first Ethernet device and said second Ethernet device remains active during said changing of said timing role.

20. The system according to claim 8, wherein said Ethernet device remains IEEE 802.3 master before, during, and after said changing said timing role.