Patents by Inventor Xiaowei Jiang

Xiaowei Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140347912
    Abstract: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: SANDISK 3D LLC
    Inventors: Chang Siau, Xiaowei Jiang, Yingchang Chen
  • Patent number: 8898390
    Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Xiaowei Jiang, Li Zhao, Ravishankar Iyer
  • Patent number: 8804744
    Abstract: A method for data transmission based on a relay mobile communication system and an equipment thereof are provided by the present invention. The method includes: at least two transport planes are configured on the Un interface protocol stack of the relay equipment and the base station eNode B; the relay equipment and the eNode B transmit the data via at least two transport planes configured on the Un interface protocol stack. With the present invention, the throughput rate of the Un interface between the relay equipment and the eNode B in the relay mobile communication system is improved, and the time delay of the Un interface is reduced.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 12, 2014
    Assignee: China Mobile Communications Corporation
    Inventors: Youjun Gao, Zhenping Hu, Ning Yang, Weimin Wu, Desheng Wang, Xiaowei Jiang
  • Publication number: 20140204105
    Abstract: Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request includes video data. A compression of the video data may be conducted to obtain compressed data, wherein the compression of the video data is transparent to the motion compensation module. In addition, the compressed data can be stored to one or more memory chips. Moreover, a read request may be received, wherein stored data is retrieved from at least one of the one or more memory chips in response to the request. Additionally, a decompression of the stored data may be conducted to obtain decompressed data.
    Type: Application
    Filed: December 21, 2011
    Publication date: July 24, 2014
    Inventors: Zhen Fang, Nitin B. Gupte, Xiaowei Jiang
  • Publication number: 20140195489
    Abstract: Architecture that addresses an end-to-end solution for logical transactional replication from a shared-nothing clustered database management system, which uses adaptive cloning for high availability. This can be time based using a global logical timestamp. The disclosed architecture, used for refreshing stale clones, does not preserve user transaction boundaries, which is a more complex situation than where the boundaries are preserved. In such a scenario it is probable that for a given data segment no clone of the segment may contain the complete user transaction history, and hence, the history has to be pieced together from the logs of multiple different clones. This is accomplished such that log harvesting is coordinated with the clone state transitions to ensure the correctness of logical replication.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 10, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Rui Wang, Michael E. Habben, Qun Guo, Peter Byrne, Robin D. Dhamankar, Vishal Kathuria, Mahesh K. Sreenivas, Yixue Zhu, Xiaowei Jiang
  • Patent number: 8671074
    Abstract: Architecture that addresses an end-to-end solution for logical transactional replication from a shared-nothing clustered database management system, which uses adaptive cloning for high availability. This can be time based using a global logical timestamp. The disclosed architecture, used for refreshing stale clones, does not preserve user transaction boundaries, which is a more complex situation than where the boundaries are preserved. In such a scenario it is probable that for a given data segment no clone of the segment may contain the complete user transaction history, and hence, the history has to be pieced together from the logs of multiple different clones. This is accomplished such that log harvesting is coordinated with the clone state transitions to ensure the correctness of logical replication.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: March 11, 2014
    Assignee: Microsoft Corporation
    Inventors: Rui Wang, Michael E. Habben, Qun Guo, Peter Byrne, Robin D. Dhamankar, Vishal Kathuria, Mahesh K. Sreenivas, Yixue Zhu, Xiaowei Jiang
  • Publication number: 20140019736
    Abstract: In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
    Type: Application
    Filed: December 30, 2011
    Publication date: January 16, 2014
    Inventors: Xiaowei Jiang, Srihari Makineni, Zhen Fang, Dmitri Pavlov, Ravi Iyer
  • Publication number: 20130326101
    Abstract: An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an interrupt handling instruction. Storage circuitry to hold different sets of micro-ops where each set of micro-ops is to handle a different interrupt. First logic circuitry to execute a set of said sets of micro-ops to handle an interrupt that said set is designed for. Second logic circuitry to return program flow to an invoking program upon said first logic circuitry having handled said interrupt.
    Type: Application
    Filed: December 22, 2011
    Publication date: December 5, 2013
    Inventors: Zhen Fang, Xiaowei Jiang, Shihari Makineni, Ramesh G. Illikkal, Ravishankar Iyer
  • Publication number: 20130311738
    Abstract: An apparatus is described that contains a processing core comprising a CPU core and at least one accelerator coupled to the CPU core. The CPU core comprises a pipeline having a translation look aside buffer. The CPU core comprising logic circuitry to set a lock bit in attribute data of an entry within the translation look-aside buffer entry to lock a page of memory reserved for the accelerator.
    Type: Application
    Filed: March 30, 2012
    Publication date: November 21, 2013
    Inventors: Xiaowei Jiang, Hongliang Gao, Zhen Fang, Srihari Makineni, Ravishankar Iyer
  • Publication number: 20120230248
    Abstract: A method for data transmission based on a relay mobile communication system and an equipment thereof are provided by the present invention. The method includes: at least two transport planes are configured on the Un interface protocol stack of the relay equipment and the base station eNode B; the relay equipment and the eNode B transmit the data via at least two transport planes configured on the Un interface protocol stack. With the present invention, the throughput rate of the Un interface between the relay equipment and the eNode B in the relay mobile communication system is improved, and the time delay of the Un interface is reduced.
    Type: Application
    Filed: October 13, 2010
    Publication date: September 13, 2012
    Applicant: CHINA MOBILE COMMUNICATIONS CORPORATION
    Inventors: Youjun Gao, Zhenping Hu, Ning Yang, Weimin Wu, Desheng Wang, Xiaowei Jiang
  • Publication number: 20120233393
    Abstract: In one embodiment, a processor includes a first cache and a second cache, a first core associated with the first cache and a second core associated with the second cache. The caches are of asymmetric sizes, and a scheduler can intelligently schedule threads to the cores based at least in part on awareness of this asymmetry and resulting cache performance information obtained during a training phase of at least one of the threads.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 13, 2012
    Inventors: Xiaowei Jiang, Li Zhao, Ravishankar Iyer
  • Patent number: 8078582
    Abstract: Aspects of the subject matter described herein relate to data change ordering in multi-log based replication. In aspects, local seeds are maintained for subtransactions involved in a transaction, where each subtransaction may occur on a different node that hosts one or more database fragments involved in the transaction. When a subtransaction communicates with another subtransaction in a transaction, the subtransaction sends its local seed to the other subtransaction. The receiving subtransaction compares its local seed with the received seed and updates its local seed if the received seed is logically after its local seed. A subtransaction uses a local seed to generate sequence identifiers for changes made by the subtransaction. These identifiers allow data changes of a transaction that are made on multiple nodes to be partially ordered relative to other changes made during the transaction.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: December 13, 2011
    Assignee: Microsoft Corporation
    Inventors: Rui Wang, Peter Byrne, Leigh M. Stewart, Robin D. Dhamankar, Qun Guo, Michael E. Habben, Xiaowei Jiang
  • Publication number: 20110251997
    Abstract: Architecture that addresses an end-to-end solution for logical transactional replication from a shared-nothing clustered database management system, which uses adaptive cloning for high availability. This can be time based using a global logical timestamp. The disclosed architecture, used for refreshing stale clones, does not preserve user transaction boundaries, which is a more complex situation than where the boundaries are preserved. In such a scenario it is probable that for a given data segment no clone of the segment may contain the complete user transaction history, and hence, the history has to be pieced together from the logs of multiple different clones. This is accomplished such that log harvesting is coordinated with the clone state transitions to ensure the correctness of logical replication.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 13, 2011
    Applicant: Microsoft Corporation
    Inventors: Rui Wang, Michael E. Habben, Qun Guo, Peter Byrne, Robin D. Dhamankar, Vishal Kathuria, Mahesh K. Sreenivas, Yixue Zhu, Xiaowei Jiang
  • Publication number: 20100306188
    Abstract: A system and method for processing database queries. An optimizer produces query plans based on queries. Query plans are stored in a persistent storage. In response to receiving a query, the system selectively retrieves a stored query plan corresponding to the query for execution. Optimization of the query may be selectively performed. A stored query plan or a new query plan may be executed. Based on metrics collected during execution, the system may automatically revert to a stored plan other than the one being executed. Based on metrics of a reverted to plan, the system may roll back to the first plan. The persistent storage enables the use of query plans after a system restart, transfer to another device, or other changes.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 2, 2010
    Applicant: Microsoft Corporation
    Inventors: Conor Cunningham, Boris Baryshnikov, Xiaowei Jiang
  • Publication number: 20100257138
    Abstract: Aspects of the subject matter described herein relate to data change ordering in multi-log based replication. In aspects, local seeds are maintained for subtransactions involved in a transaction, where each subtransaction may occur on a different node that hosts one or more database fragments involved in the transaction. When a subtransaction communicates with another subtransaction in a transaction, the subtransaction sends its local seed to the other subtransaction. The receiving subtransaction compares its local seed with the received seed and updates its local seed if the received seed is logically after its local seed. A subtransaction uses a local seed to generate sequence identifiers for changes made by the subtransaction. These identifiers allow data changes of a transaction that are made on multiple nodes to be partially ordered relative to other changes made during the transaction.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Applicant: Microsoft Corporation
    Inventors: Rui Wang, Peter Byrne, Leigh M. Stewart, Robin D. Dhamankar, Qun Guo, Michael E. Habben, Xiaowei Jiang
  • Publication number: 20050187980
    Abstract: The present invention the is directed to systems and methods for hosting the CLR in a DBMS in order to achieve reliability, scalability, security, and robustness for enabled DBMS programming features. Integrating the CLR with a DBMS enables programming features in the database such as stored procedures, functions, triggers, types, and aggregates to be written in any of the programming languages that are compiled into IL code supported by the CLR. For the various embodiments of the present invention, the CLR is hosted inside the DBMS and, instead of making requests directly to the server operating system, the CLR instead interfaces with the DBMS via DBMS APIs for such requests, and only the DBMS directly interfaces with the server operating system to access the server.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 25, 2005
    Inventors: Peter Carlin, Jose Blakeley, Balaji Rathakrishnan, Beysim Sezgin, Mason Bendixen, Xiaowei Jiang, Aakash Kambuj, Alazel Acheson