Abstract: A method for configuring a radio bearer includes: sending by a central unit protocol partitioning information for the radio bearer to be configured to a target distributed unit, in which the protocol partitioning information indicates an assignment of each protocol layer of a radio-side protocol stack between the central unit and the target distributed unit; configuring a first protocol stack by the target distributed unit according to the protocol partitioning information; sending by the target distributed unit configuration information of the first protocol stack to the central unit; and configuring a second protocol stack by the central unit according to the configuration information of the first protocol stack.

Abstract: A data transmission method includes: acquiring n RLC PDUs transmitted from an RLC layer, n being an integer greater than 1; encapsulating the indication information corresponding to the n RLC PDUs as a packet header of a MAC PDU and the n RLC PDUs as a packet body of the MAC PDU, to generate the MAC PDU, the indication information corresponding to the n RLC PDUs comprising an LCID, a sequence number, and a length corresponding to each RLC PDU; and sending the MAC PDU to a communication peer.

Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.

Abstract: The present disclosure provides a processor providing a memory architecture having M-number of processing elements each having at least N-number of processing units and a local memory. The processor comprises a first processing element of the M-number of processing elements comprising a first set of N-number of processing units configured to perform a computing operation, and a first local memory configured to store data utilized by the N-number of processing units. The processor further comprises a data hub configured to receive data from the M-number of processing elements and to provide shared data to each processing element of the M-number of processing elements.

Abstract: The present disclosure provides systems and methods for executing instructions. The system can include: processing unit having a core configured to execute instructions; and a host unit configured to: compile computer code into a plurality of instructions that includes a set of instructions that are determined to be executed in parallel on the core, wherein the set of instructions each includes an operation instruction and an indication bit and wherein the indication bit is set to identify the last instruction of the set of instructions, and provide the set of instructions to the core.

Abstract: The present disclosure relates to a unified memory apparatus having a unified storage medium and one or more processing units. The unified memory apparatus can include a first storage module having a first plurality of storage cells, and a second storage module having a second plurality of storage cells, each of the first and second plurality of storage cells configured to store data and to be identified by a unique cell identifier. The one or more processing units are in communication with the unified storage medium and the processing units are configured to receive a first input data from one of the first plurality of storage cells, receive a second input data from one of the second plurality of storage cells, and generate an output data based on the first and second input data.

Abstract: An integrated circuit including a data architecture including N adders and N multipliers configured to receive operands. The data architecture receives instructions for selecting a data flow between the N multipliers and the N adders of the data architecture. The selected data flow includes the options: (1) a first data flow using the N multipliers and the N adders to provide a multiply-accumulate mode and (2) a second data flow to provide a multiply-reduce mode.

Abstract: The present disclosure relates to a computing device with a multiple pipeline architecture. The multiple pipeline architecture comprises a first and second pipeline for which are concurrently running, where the first pipeline runs at least one cycle ahead of the second pipeline. Special number detection is utilized on the first pipeline, where a special number is a numerical value which yields a predictable result. Upon the detection of a special number, a computation is optimized.

Abstract: One embodiment facilitates a write operation in a shingled magnetic recording device. During operation, the system receives, by a controller module of the device, a request to write first data, wherein the device has a plurality of bands with overlapping tracks for storing data. In response to determining that the first data is updated data corresponding to original data stored in a first band, the system appends the updated data to a second band with available storage space. The system merges the updated data with the original data.

Abstract: The processing load on a host processor is substantially reduced by offloading the transport layer security protocol, such as the TLS/SSL protocol, the transport layer protocol stack, such as the TCP/IP protocol stack, and the network control required to access a network, such as the Internet, onto an expansion device.

Abstract: Systems and methods for efficiently protecting simultaneous access to user-space shared data by multiple threads using a kernel structure is disclosed. Further, a mechanism within a spinlock allows reduction of the performance and power interference associated with the improved spinlock. This allows a thread in the critical section to complete its execution sooner by increasing the frequency and voltage of the CPU core it runs on. The improved spinlock allows a thread to enter a power saving state and the critical section to instruct a PCU to allocate a headroom power budget exclusively to the core that executed the instruction. The improved spinlock also provides saving in dynamic power during clock gated of the CPU resources and dynamic and static power during power gated of the CPU resources.

Abstract: A system and method of a snoop filter providing larger address space coverage, freeing back-invalidation when an entry is evicted, and freeing excessive snoops when a snoop has a miss is provided. The snoop filter tracks the addresses of upper level cache lines at region basis, which enables a relatively smaller snoop filter with much larger address space coverage. The snoop filter is non-inclusive. The snoop filter is designed such that each upper level cache has its own bloom filter to track address space occupancy, eliminating a significant portion of conflict misses. The snoop filter is designed at a larger granularity such that applications have a much better spatial locality. The larger granularity employs coarse grain tracking techniques, which allow monitor of large regions of memory and use that infoiivation to avoid unnecessary broadcasts and filter unnecessary cache tag lookups, thus improving system performance and power consumption.

Abstract: A computer system of a service provider includes a processing unit executing a thread issued by a user and a random access memory (RAM) cache disposed external to the processing unit and operatively coupled to the processing unit to store data accessed or to be accessed by the processing unit. The processing unit includes control circuitry configured to, in response to receiving an access request while the thread is being executed, determine whether the thread is allowed to access the RAM cache according to a service level agreement (SLA) level established between the service provider and the user, and when the thread is RAM cacheable, access the RAM cache.

Abstract: The present application provides methods and systems for memory management of a kernel space and a user space. An exemplary system for memory management of the kernel space and the user space may include a first storing unit configured to store a first root page table index corresponding to the kernel space. The system may also include a second storing unit configured to store a second root page table index corresponding to the user space. The system may further include a control unit communicatively coupled to the first and second registers and configured to: translate a first virtual address to a first physical address in accordance with the first root page table index for an operating system kernel, and translate a second virtual address to a second physical address in accordance with the second root page table index for a user process.

Abstract: One embodiment facilitates a write operation in a shingled magnetic recording device. During operation, the system receives, by a controller module of the device, a request to write first data, wherein the device has a plurality of bands with overlapping tracks for storing data. In response to determining that the first data is updated data corresponding to original data stored in a first band, the system appends the updated data to a second band with available storage space. The system merges the updated data with the original data.

Abstract: A System-on-Chip (SoC) performs secure communication operations. The SoC may include a peripheral interface configured to communicate with a host system. The SoC may also include a network interface configured to receive network packets in a secure communication session. The SoC may further include a processor configured to execute an Operating System (OS) software and a secure communication software stack to process at least one received network packet in the secure communication session. In addition, the SoC may include a secure communication engine configured to perform cryptographic operations and generate at least one decrypted packet in the secure communication session. The at least one decrypted packet may be provided to the host system via the peripheral interface.

Abstract: Embodiments of the disclosure provide a virtual switch device and method for distributing packets. A peripheral card can include a peripheral interface configured to communicate with a host system having a controller, receiving one or more packets from the host system; a processor unit configured to process the packets according to configuration information provided by the controller; a packet processing engine configured to route the packets according to a flow table established via the processor unit; and a network interface configured to distribute the routed packets.

Abstract: A multi-core CPU includes a Last-Level Cache (LLC) interconnected with a plurality of cores. The LLC may include a shared portion and a private portion. The shared portion may be shared by the plurality of cores. The private portion may be connected to a first core of the plurality of cores and may be exclusively assigned to the first core. The first core may be configured to initiate a data access request to access data stored in the LLC and initiate a data access request to access data stored in the LLC. The first core may route the data access request to the private portion based on the determination that the data access request is the TLS type of access request and route the data access request to the shared portion based on the determination that the data access request is not the TLS type of access request.

Abstract: An apparatus for operating a storage system is provided. The apparatus is coupled with one or more storage devices and one or more controllers and comprises a data request input module configured to receive a request for data and determine a data stripe that includes the requested data. The apparatus further comprises a controller instruction module configured to instruct one or more controllers to perform a decoding of code words of the determined data stripe, wherein the code words are acquired by the controllers from the one or more storage devices, and determine, based on error status information associated with the decoding, an error handling operation on the data stripe to modify one or more code words of the data stripe. The apparatus also comprises a data packaging module configured to generate the requested data based on the modified at least one or more code words.

Abstract: The present invention discloses a method for automatically detecting door or window faults, comprising the following steps: mounting a displacement sensor at at least one monitoring position of the door or window frame and leaf and/or door or window hardware to monitor a relative position change of the door or window frame and leaf and/or relative displacement of the hardware at said at least one monitoring position; and connecting the displacement sensor to a controller which judges whether the relative position change of the door or window frame and leaf and/or relative displacement of the hardware at said at least one monitoring position exceeds a displacement threshold, and thereby perform combined judgment for door or window faults. The present invention further discloses a mechanism for automatically detecting door or window faults.