Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: The invention discloses an alignment method of a liquid crystal display panel including the following steps: assembling a color filter substrate, an array substrate and a liquid crystal layer into a liquid crystal display panel; applying a first alignment voltage to a common electrode line layer of the array substrate, applying a second alignment voltage to a common electrode layer of the color filter substrate, and a predetermined voltage difference existed between the first alignment voltage and the second alignment voltage; performing alignment to the liquid crystal layer of the liquid crystal display panel by the predetermined voltage difference, to make liquid crystal molecules in the liquid crystal layer arranged with a preset tilt angle; and irradiating the liquid crystal layer with an ultraviolet ray. The effect of alignment can be improved, the dependence of liquid crystal alignment on the data line can be reduced, and improves the product yield.

Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: A GOA drive circuit includes a multiple stage of GOA drive units. A GOA drive unit includes a pre-pulldown unit which is configured to disconnect a discharge path of a first voltage signal via the pull-down sustaining unit before the first voltage signal jumps from a low electric potential to a high electric potential. In the GOA drive circuit, the voltage stability of the key nodes in a circuit and the reliability of the timing can be ensured; overall performance of the GOA drive circuit can be improved; and a service life of a display device can be prolonged.

Abstract: The invention provides a GOA circuit, other than the first to the fourth GOA units, in each GOA unit: the first pull-down maintenance module receives the first control signal, low voltage signal, scan signal and circuit start signal, and is connected to the first node, wherein the 52nd TFT of the first pull-down maintenance module has a gate connected to the first node, a source receives the circuit start signal, and a drain connected to the gates of the 31st TFT and 41st TFT so that when the first node is at high voltage, the gate-source voltage difference of the 31st TFT and the 41st TFT are both negative to effectively reduce the current leakage and prevent the current leakage from affecting the voltage of the first node, to improve the circuit stability without additional signal lines, able to facilitate production cost reduction and achieving narrow border design.

Abstract: A method of improving a high current of GOA circuit when power on is provided, including: determining a GOA circuit, wherein the GOA circuit includes a plurality of GOA structure units in cascade, each of GOA structure units includes a pull-up control circuit, a pull-up circuit, a transfer circuit, a pull-down circuit, a pull-down holding circuit and a bootstrapping capacitor, and a pre-charge signal, a first clock signal and a second clock signal are disposed on each of GOA structure units; and pulling up a voltage of the first clock signal and the second clock signal to a predetermined value for a certain time at an abnormal power off moment to discharge the pre-charge signal when detecting the GOA circuit abnormally power off. By practice of the disclosure, the pre-charge signal of GOA structure unit could discharge when the GOA circuit abnormally power off to reduce the high current probability.

Abstract: Disclosed is a manufacturing method of an array substrate, comprising steps of: depositing a first metal layer on a substrate; depositing a gate insulating layer on the substrate and the first metal layer, and forming a first via hole in the in-plane region of the gate insulating layer; depositing a second metal layer in an in-plane region and an out-of-plane of the gate insulating layer, wherein the second metal layer located in the in-plane region fills the first via hole; depositing a passivation layer on the second metal layer and the gate insulating layer, and forming a second via hole in the in-plane region of the passivation layer; forming a third via hole and a fourth via hole in the out-of plane region of the passivation layer, respectively; depositing a transparent conductive layer in the in-plane region and in the out-of-plane region of the passivation layer, respectively.

Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.

Abstract: The invention provides a GOA circuit, other than the first to the fourth GOA units, in each GOA unit: the first pull-down maintenance module receives the first control signal, low voltage signal, scan signal and circuit start signal, and is connected to the first node, wherein the 52nd TFT of the first pull-down maintenance module has a gate connected to the first node, a source receives the circuit start signal, and a drain connected to the gates of the 31st TFT and 41st TFT so that when the first node is at high voltage, the gate-source voltage difference of the 31st TFT and the 41st TFT are both negative to effectively reduce the current leakage and prevent the current leakage from affecting the voltage of the first node, to improve the circuit stability without additional signal lines, able to facilitate production cost reduction and achieving narrow border design.

Abstract: The invention discloses an alignment method of a liquid crystal display panel including the following steps: assembling a color filter substrate, an array substrate and a liquid crystal layer into a liquid crystal display panel; applying a first alignment voltage to a common electrode line layer of the array substrate, applying a second alignment voltage to a common electrode layer of the color filter substrate, and a predetermined voltage difference existed between the first alignment voltage and the second alignment voltage; performing alignment to the liquid crystal layer of the liquid crystal display panel by the predetermined voltage difference, to make liquid crystal molecules in the liquid crystal layer arranged with a preset tilt angle; and irradiating the liquid crystal layer with an ultraviolet ray. The effect of alignment can be improved, the dependence of liquid crystal alignment on the data line can be reduced, and improves the product yield.

Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.

Abstract: Disclosed is a manufacturing method of an array substrate, comprising steps of: depositing a first metal layer on a substrate; depositing a gate insulating layer on the substrate and the first metal layer, and forming a first via hole in the in-plane region of the gate insulating layer; depositing a second metal layer in an in-plane region and an out-of-plane of the gate insulating layer, wherein the second metal layer located in the in-plane region fills the first via hole; depositing a passivation layer on the second metal layer and the gate insulating layer, and forming a second via hole in the in-plane region of the passivation layer; forming a third via hole and a fourth via hole in the out-of plane region of the passivation layer, respectively; depositing a transparent conductive layer in the in-plane region and in the out-of-plane region of the passivation layer, respectively.

Abstract: A GOA drive circuit includes a multiple stage of GOA drive units. A GOA drive unit includes a pre-pulldown unit which is configured to disconnect a discharge path of a first voltage signal via the pull-down sustaining unit before the first voltage signal jumps from a low electric potential to a high electric potential. In the GOA drive circuit, the voltage stability of the key nodes in a circuit and the reliability of the timing can be ensured; overall performance of the GOA drive circuit can be improved; and a service life of a display device can be prolonged.

Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.

Abstract: The invention provides a GOA circuit, comprising a plurality of cascaded GOA units. Each GOA unit comprises: a pull up control module, an output module, a pull down module and a pull down maintenance module; for N-th GOA unit: the 41st TFT of pull down module having a gate receiving a scan signal from (N+4)-th GOA unit, a source connected to a circuit start signal, and a drain connected to the first node, and the circuit start signal having a low voltage level lower than or equal to 0V and higher than the low voltage signal; so that when the scan signal from (N+4)-th GOA unit changing from high voltage to low voltage, the gate-source voltage difference of the 41st TFT being negative to effectively reduce the current leakage and prevent the current leakage from affecting the first node voltage, improve circuit stability, facilitate cost reduction and narrow border.

Abstract: This disclosure provides a test circuit for a display panel and a display device. The test circuit for the display panel comprises one or more shorting bars, a plurality of signal lines, and a switch circuit connected with the shorting bars and the signal lines. The switch circuit establishes a connection between the signal lines and a corresponding shorting bar when the display panel is tested, and the switch circuit cuts off the connection between the signal lines and the corresponding shorting bar when the display panel is not tested.

Abstract: The present disclosure is about a Gate Driver on Array (GOA) circuit, its driving method, and a display panel employing the circuit. The GOA circuit has a node between its pull-up control circuit and pull-up circuit where a reference voltage is introduced. A reset circuit has its input terminal connected to the node, its output terminal connected to the reference voltage and its control terminal is applied an activation signal STV at the instant when the display panel is shutdown so as to bring down the node's level.

Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.

Abstract: A GOA circuit includes a plurality of cascaded GOA units. An N-th stage GOA unit controls charging of an N-th horizontal scanning line. The N-th stage GOA unit includes a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor (Cb). The pull-high unit, the pull-down sustain unit and the boast capacitor (Cb) are connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit and the pull-down unit are connected with the first node (Q(N)) of the N-th stage GOA unit. The pull-down sustain unit includes a first TFT (T61), a second TFT (T62), a third TFT (T64), a fourth TFT (T43), and a fifth TFT (T33). Also provided is a liquid crystal display device using the GOA circuit.

Abstract: A thin-film transistor (TFT) array substrate includes a TFT arrangement and a storage capacitor. A gate insulation layer has a portion interposed between two electrode plates of the storage capacitor and thinner than a remaining portion of the gate insulation layer and thus, the thickness of insulation between the electrode plates of the storage capacitor is reduced so that the area of the opposite surfaces of the capacitor can be made smaller and an increased aperture ratio can be achieved.