Abstract: A method is provided for manufacturing a thin film transistor array substrate, which includes: a substrate on which a thin film transistor and a storage capacitor are formed on the substrate. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.

Abstract: A method of improving a high current of GOA circuit when power on is provided, including: determining a GOA circuit, wherein the GOA circuit includes a plurality of GOA structure units in cascade, each of GOA structure units includes a pull-up control circuit, a pull-up circuit, a transfer circuit, a pull-down circuit, a pull-down holding circuit and a bootstrapping capacitor, and a pre-charge signal, a first clock signal and a second clock signal are disposed on each of GOA structure units; and pulling up a voltage of the first clock signal and the second clock signal to a predetermined value for a certain time at an abnormal power off moment to discharge the pre-charge signal when detecting the GOA circuit abnormally power off. By practice of the disclosure, the pre-charge signal of GOA structure unit could discharge when the GOA circuit abnormally power off to reduce the high current probability.

Abstract: Disclosed is a GOA drive circuit, which includes multiple stages of GOA drive units. A pull-down unit of a GOA drive unit in each stage is configured to increase a time for a first voltage signal to be pulled down to a first electric potential during a process when the first voltage signal jumps from a high electric potential to a low electric potential, so as to enable the first voltage signal to have a stepwise falling edge. In the GOA drive circuit, smoothness of a voltage at a key node thereof during a voltage changing process can be ensured, whereby an output performance of the GOA drive circuit can be improved, and an overall performance thereof can be improved accordingly.

Abstract: Disclosed is a liquid crystal display panel. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.

Abstract: The invention provides a GOA circuit, each GOA unit of GOA circuit comprising: a pull up control module, an output module, a pull down module, a first pull down maintenance module, and a second pull down maintenance module; wherein the 32nd TFT of first pull down maintenance module and the 33rd TFT of second pull down maintenance module having gate connected to the second node and third node respectively, source connected to the first low voltage signal, and drain connected to the scan signal; the 42nd TFT of first pull down maintenance module, the 43rd TFT of second pull down maintenance module, and the 41st TFT of pull down module having source connected to the second low voltage signal. The first low voltage signal is higher than the second low voltage signal, and the second low voltage signal is higher than low voltage level of the clock signal.

Abstract: The invention provides a GOA circuit, each GOA unit of GOA circuit comprising: a pull up control module, an output module, a pull down module, a first pull down maintenance module, and a second pull down maintenance module; wherein the 32nd TFT of first pull down maintenance module and the 33rd TFT of second pull down maintenance module having gate connected to the second node and third node respectively, source connected to the first low voltage signal, and drain connected to the scan signal; the 42nd TFT of first pull down maintenance module, the 43rd TFT of second pull down maintenance module, and the 41st TFT of pull down module having source connected to the second low voltage signal. The first low voltage signal is higher than the second low voltage signal, and the second low voltage signal is higher than low voltage level of the clock signal.

Abstract: The present invention provides a test circuit of gate driver on array (GOA) and a test method of GOA. The test circuit of GOA comprises a first wiring arranged outside the area where the plurality of display panels is located; a second wiring located between two of the adjacent regions; a switch unit arranged between the first wiring and the second wiring, wherein the area is divided into a plurality of areas where the display panel is located.

Abstract: The invention provides a GOA circuit, comprising a plurality of cascaded GOA units. Each GOA unit comprises: a pull up control module, an output module, a pull down module and a pull down maintenance module; for N-th GOA unit: the 41st TFT of pull down module having a gate receiving a scan signal from (N+4)-th GOA unit, a source connected to a circuit start signal, and a drain connected to the first node, and the circuit start signal having a low voltage level lower than or equal to 0V and higher than the low voltage signal; so that when the scan signal from (N+4)-th GOA unit changing from high voltage to low voltage, the gate-source voltage difference of the 41st TFT being negative to effectively reduce the current leakage and prevent the current leakage from affecting the first node voltage, improve circuit stability, facilitate cost reduction and narrow border.

Abstract: A thin-film transistor array panel and a manufacturing method thereof are disclosed. The thin-film transistor array panel has a polysilicon layer including a first region, a second region and a third region. The second region includes a fourth region, a fifth region and a sixth region. The third region includes a seventh region, an eighth region and ninth region. The sixth, the fourth, the ninth and the seventh regions are doped with first, second, third and fourth ions, respectively. In a thin-film transistor of the thin-film transistor array panel, a gate electrode, a source electrode and a drain electrode thereof correspond to the first, the sixth and the ninth regions, respectively. The device is able to reduce leakage current in the thin-film transistor.

Abstract: The disclosure discloses a thin film transistor and a manufacturing method thereof, a liquid crystal display panel, a transition pattern is disposed between a doping pattern and a source electrode pattern, the transition pattern covers sidewalls of the source electrode pattern and the drain electrode pattern respectively to insulate an active pattern and the sidewalls of the source electrode pattern and the drain electrode pattern in direct contact, so as to reduce leakage current of a TFT. Moreover, two sides of the transition pattern adjacent to the active pattern are covered by the doping pattern, which can reduce contact impendence of the active pattern and the source electrode pattern as well as the drain electrode pattern, so as to prevent the problem of insufficient charge of the TFT.

Abstract: Disclosed is a liquid crystal display panel and a method for manufacturing the same. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.

Abstract: The present invention involves a GOA circuit and a liquid crystal device. The GOA circuit comprises a plurality of cascaded GOA units. An N-th stage GOA unit controls charging of an N-th horizontal scanning line. The N-th stage GOA unit comprises a pull-high control unit, a pull-high unit, a pull-down unit, a pull-down sustain unit, and a boast capacitor (Cb). The pull-high unit, the pull-down sustain unit and the boast capacitor (Cb) are respectively connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit and the pull-down unit are respectively connected with the first node (Q(N)) of the N-th stage GOA unit. The pull-down sustain unit comprises a first TFT (T61), a second TFT (T62), a third TFT (T64), a fourth TFT (T43), and a fifth TFT (T33). The present invention also provides a corresponding liquid crystal display device.

Abstract: The present disclosure provides a gate driver on array (GOA) driving circuit and a liquid crystal display (LCD) device. The GOA driving circuit comprises a plurality of cascaded GOA units. An Nth cascaded GOA unit outputs a gate driving signal to an Nth horizontal scanning line Gn of an display area. The Nth cascaded GOA unit comprises a pull-up assembly, a pull-up control assembly, a pull-down maintaining assembly, a download assembly and a bootstrap capacitor assembly.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, and a light shielding layer. The first substrate includes a first display area and a first non-display area surrounding the first display area. The second substrate is opposite to the first substrate. The second substrate includes a second display area and a second non-display area surrounding the second display area. The light shielding layer overlaps at least one part of at least one of the first display area and the second display area.

Abstract: This disclosure provides a test circuit for a display panel and a display device. The test circuit for the display panel comprises one or more shorting bars, a plurality of signal lines, and a switch circuit connected with the shorting bars and the signal lines. The switch circuit establishes a connection between the signal lines and a corresponding shorting bar when the display panel is tested, and the switch circuit cuts off the connection between the signal lines and the corresponding shorting bar when the display panel is not tested.

Abstract: The present invention provides a test circuit of gate driver on array (GOA) and a test method of GOA. The test circuit of GOA comprises a first wiring arranged outside the area where the plurality of display panels is located; a second wiring located between two of the adjacent regions; a switch unit arranged between the first wiring and the second wiring, wherein the area is divided into a plurality of areas where the display panel is located.

Abstract: The present disclosure is about a Gate Driver on Array (GOA) circuit, its driving method, and a display panel employing the circuit. The GOA circuit has a node between its pull-up control circuit and pull-up circuit where a reference voltage is introduced. A reset circuit has its input terminal connected to the node, its output terminal connected to the reference voltage and its control terminal is applied an activation signal STV at the instant when the display panel is shutdown so as to bring down the node's level.

Abstract: A gate driver on array (GOA) driver circuit and a liquid crystal display are proposed. The GOA driver circuit includes cascaded GOA units. A gate driver signal is output to an Nth-stage horizontal scan line Gn on a display zone according to an Nth-stage GOA unit output gate driver signal. The Nth-stage GOA unit includes a pull-up module, a pull-up control module, a pull-down holding module, a transferring module, and a bootstrap capacitor module.

Abstract: A gate driver on array (GOA) driver circuit and a liquid crystal display are proposed. The GOA driver circuit includes cascaded GOA units. A gate driver signal is output to an Nth-stage horizontal scan line Gn on a display zone according to an Nth-stage GOA unit output gate driver signal. The Nth-stage GOA unit includes a pull-up module, a pull-up control module, a pull-down holding module, a transferring module, and a bootstrap capacitor module.

Abstract: A gate driver on array (GOA) driver circuit and a liquid crystal display are proposed. The GOA driver circuit includes cascaded GOA units. The Nth-stage GOA unit includes a pull-up module, a pull-up control module, a pull-down holding module, a transferring module, and a bootstrap capacitor module. The pull-up module, the pull-down holding module, and the bootstrap capacitor module are electrically connected to an Nth-stage gate signal node Qn and an Nth-stage horizontal scan line Gn, respectively. The pull-up control module and the transferring module are connected to the Nth-stage gate signal node Qn.