Abstract: The present disclosure is directed towards a method, system, and apparatus for distinguishing between isotopically substituted liquids, such as H2O and D2O, and sensing other isotopologues of water, such as H218O. In an embodiment, the electrical output characteristics of the apparatus or device are used as diagnostic signals to distinguish between isotopic compositions and isotopologues of a liquid. In an embodiment, water droplets with volume of several micro litre are applied to the apparatus or device generating some electrical signals which show differences between the application of H2O and D2O, for example. One advantage of the present method and system is that the configuration is simple and portable, with no need for complicated equipment and operation protocols.

Abstract: Write heads may be formed by reactive ion etching (RIE) a dielectric mask and then reactive ion etching a polymeric underlayer. The first RIE affects the second RIE. The first portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 1.3 to 2, a gas flow ratio of CF4 to He between 2.2 and about 3, and a ratio of RF source power to RF bias power between about 10 and about 16. The second portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 0.3 to 0.8, a gas flow ratio of CF4 to He between about 1.2 and about 1.8, and a ratio of RF source power to RF bias between about 22 to 28. With the above parameters, the dielectric mask can be formed with minimized damage on the underlayer.

Abstract: Write heads may be formed by reactive ion etching (RIE) a dielectric mask and then reactive ion etching a polymeric underlayer. The first RIE affects the second RIE. The first portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 1.3 to 2, a gas flow ratio of CF4 to He between 2.2 and about 3, and a ratio of RF source power to RF bias power between about 10 and about 16. The second portion of the first RIE process is performed with a ratio of CF4 to CHF3 between about 0.3 to 0.8, a gas flow ratio of CF4 to He between about 1.2 and about 1.8, and a ratio of RF source power to RF bias between about 22 to 28. With the above parameters, the dielectric mask can be formed with minimized damage on the underlayer.

Abstract: A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries.

Abstract: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.

Abstract: Process kits for use in a semiconductor process chambers have been provided herein. In some embodiments, a process kit for a semiconductor process chamber includes a body configured to rest about a periphery of a substrate support and having sidewalls defining an opening corresponding to a central region of the substrate support. A lip extends from the sidewalls of the body into the opening, wherein a portion of an upper surface of the lip is configured to be disposed beneath a substrate during processing. A first distance measured between opposing sidewalls of the body is greater than a width across the upper surface of a substrate to be disposed within the opening by at least about 7.87 mm.

Abstract: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.

Abstract: Methods for forming an ultra thin structure. The method includes a polymer deposition and etching process. In one embodiment, the methods may be utilized to form fabricate submicron structure having a critical dimension less than 30 nm and beyond. The method further includes a multiple etching processes. The processes may be varied to meet different process requirements. In one embodiment, the process gently etches the substrate while shrinking critical dimension of the structures formed within the substrate. The dimension of the structures may be shank by coating a photoresist like polymer to sidewalls of the formed structure, but substantially no polymer accumulation on the bottom surface of the formed structure on the substrate. The embodiments described herein also provide high selectivity in between each layers formed on the substrate during the fabricating process and preserving a good control of profile formed within the structure.

Abstract: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power and/or HF and/or LF bias power to the electrodes at the ceiling and/or the electrostatic chuck.

Abstract: A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a first polymerizing etch process gas through a radially inward one of plural concentric gas injection zones in the ceiling electrode and injecting a second polymerizing etch process gas through a radially outward one of the plural concentric gas injection zones in the ceiling electrode, the compositions of the first and second process gases having first and second carbon-to-fluorine ratios that differ from one another.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A plasma etch process includes injecting process gases with different compositions of chemical species through different radial gas injection zones of an overhead electrode to establish a desired distribution of chemical species among the plural gas injection zones.

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.

Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Abstract: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power and/or HF and/or LF bias power to the electrodes at the ceiling and/or the electrostatic chuck.

Abstract: A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries.

Abstract: A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through at least one of plural concentric gas injection zones of the ceiling electrode and injecting an inert diluent gas through at least a selected one of the plural gas injection zones of the ceiling electrode and apportioning respective flow rates of the diluent gas through respective ones of the gas injection zones in accordance with the distribution among corresponding concentric zones of the workpiece of etch profile tapering.