Abstract: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power and/or HF and/or LF bias power to the electrodes at the ceiling and/or the electrostatic chuck.

Abstract: A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries.

Abstract: The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 ?/min.

Abstract: In some implementations, a method is provided in a plasma processing chamber for stabilizing etch-rate distributions during a process transition from one process step to another process step. The method includes performing a pre-transition compensation of at least one other process parameter so as to avoid unstable plasma states by inhibiting formation of a parasitic plasma during the process transition. In some implementations, a method is provided for processing a workpiece in plasma processing chamber, which includes inhibiting deviations from an expected etch-rate distribution by avoiding unstable plasma states during a process transition from one process step to another process step.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: In some implementations, a method is provided for inhibiting charge damage in a plasma processing chamber during a process transition from one process step to another process step, including performing a pre-transition compensation of at least one process parameter so as to inhibit charge damage from occurring during the process transition. In some implementations, a method is provided for inhibiting charge damage during a process transition from one process step to another process step, which includes changing at least one process parameter with a smooth non-linear transition. In some implementations, a method is provided which includes sequentially changing selected process parameters such that a plasma is able to stabilize after each change prior to changing a next selected process parameter.

Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor workpiece, an overhead electrode overlying said workpiece support, the electrode comprising a portion of said chamber wall, an RF power generator for supplying power at a frequency of said generator to said overhead electrode and capable of maintaining a plasma within said chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that said overhead electrode and the plasma formed in said chamber at said desired plasma ion density resonate together at an electrode-plasma resonant frequency, said frequency of said generator being at least near said electrode-plasma resonant frequency.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocargon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.

Abstract: The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 ?/min.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: A method of fabricating an interconnect structure (e.g., dual damascene interconnect structure, and the like) of an integrated circuit device is disclosed. The interconnect structure is fabricated using a bi-layer mask comprising an imaging film and an organic planarizing film. The bi-layer mask is used to remove lithographic misalignment between a contact hole, a trench, and an underlying conductive line when the interconnect structure is formed. Additionally, a sacrificial layer may be used to protect an inter-metal dielectric (IMD) layer during subsequent planarization of the interconnect structure. The sacrificial layer may be formed of amorphous silicon (Si), titanium nitride (TiN), tungsten (W), and the like. The interconnect structure may be formed of a metal (e.g., copper (Cu), aluminum (Al), tantalum (Ti), tungsten (W), titanium (Ti), and the like) or a conductive compound (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), and the like).

Abstract: A method of treating a dielectric layer having a low dielectric constant, where the dielectric layer has been processed in a manner that causes a change in the dielectric constant of an affected region of the layer. The treatment of the affected region may comprise etching, sputtering, annealing, or combinations thereof. The treatment returns the dielectric constant of the dielectric layer to substantially the dielectric constant that existed before processing.