Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.

Abstract: The present invention provides a dielectric etch process with good etch rate, good selectivity with respect to photoresist mask, and much reduced striation as compared with conventional dielectric etching processes having comparable etch rate and selectivity. In one embodiment of the present invention, the dielectric layer is formed on a substrate with an underlying layer of another material and an overlying photoresist mask. A process for etching the dielectric layer comprises introducing a novel process gas into a process zone and maintaining a plasma of the process gas for a period of time. The process gas comprises a fluorocarbon gas, oxygen, a hydrogen-containing gas, and, optionally, an inert gas.

Abstract: The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor support, the electrode comprising a portion of the chamber wall, an RF power generator for supplying power at a frequency of the generator to the overhead electrode and capable of maintaining a plasma within the chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that the overhead electrode and the plasma formed in the chamber at the desired plasma ion density resonate together at an electrode-plasma resonant frequency, the frequency of the generator being at least near the electrode-plasma resonant frequency. The reactor further includes a set of MERIE magnets surrounding the plasma process area overlying the wafer surface that produce a slowly circulating magnetic field which stirs the plasma to improve plasma ion density distribution uniformity.

Abstract: The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.

Abstract: The invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a gas distribution plate including a front plate in the chamber and a back plate on an external side of the front plate, the gas distribution plate comprising a gas manifold adjacent the back plate, the back and front plates bonded together and forming an assembly. The assembly includes an array of holes through the front plate and communicating with the chamber, at least one gas flow-controlling orifice through the back plate and communicating between the manifold and at least one of the holes, the orifice having a diameter that determines gas flow rate to the at least one hole. In addition, an array of pucks is at least generally congruent with the array of holes and disposed within respective ones of the holes to define annular gas passages for gas flow through the front plate into the chamber, each of the annular gas passages being non-aligned with the orifice.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a reactor chamber having a chamber wall and containing a workpiece support for holding the semiconductor workpiece, an overhead electrode overlying said workpiece support, the electrode comprising a portion of said chamber wall, an RF power generator for supplying power at a frequency of said generator to said overhead electrode and capable of maintaining a plasma within said chamber at a desired plasma ion density level. The overhead electrode has a capacitance such that said overhead electrode and the plasma formed in said chamber at said desired plasma ion density resonate together at an electrode-plasma resonant frequency, said frequency of said generator being at least near said electrode-plasma resonant frequency.

Abstract: Disclosed herein is a post-etch treatment for plasma etched metal-comprising features in semiconductor devices. The post-etch treatment significantly reduces or eliminates surface corrosion of the etched metal-comprising feature. It is particularly important to prevent the formation of moisture on the surface of the feature surface prior to an affirmative treatment to remove corrosion-causing contaminants from the feature surface. Avoidance of moisture formation is assisted by use of a high vacuum; use of an inert, moisture-free purge gas; and by maintaining the substrate at a sufficiently high temperature to volatilize moisture.