Patents by Inventor Xiaoying Guo

Xiaoying Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978105
    Abstract: Embodiments of the disclosure disclose a store system, and a method and an apparatus for processing information of clothing items for try-on. The store system comprises: a first device, deployed in a back warehouse area of a store and configured to obtain corresponding relationship between a user and information of one or more clothing items for try-on; and provide preparation prompt information based on the corresponding relationship to prepare the one or more clothing items for the user; and a fitting room, the fitting room comprising a first door and a second door, the first door configured for the user to enter and exit the fitting room, and the second door configured for delivering the one or more clothing items for try-on corresponding to the user from the back warehouse area to the fitting room.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: May 7, 2024
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Keyang Shi, Ding Sheng, Lin Bin, Jianfeng Guo, Shurong He, Didi Yao, Wei Feng, Weizhi Xie, Wei Zhu, Jianhong Wang, Menglei Jia, Xiaoying Hu
  • Patent number: 11973041
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Publication number: 20240121768
    Abstract: This disclosure relates generally to transmission resource or transmission parameters update of various types in wireless communications. Performed by a wireless terminal in a wireless network, the method including receiving a message from a wireless communication node of the wireless network, the message indicating an update to a wireless resource or a transmission parameter associated with the wireless resource, the wireless resource being previously allocated to the wireless terminal for data reception or data transmission; parsing the message based on a type of the update to the wireless resource or the transmission parameter associated with the wireless resource to obtain the update; and transmitting or receiving data, or skipping transmitting or receiving data using the wireless resource based on the update.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 11, 2024
    Applicant: ZTE Corporation
    Inventors: Mengzhu CHEN, Yuzhou Hu, Hong Tang, Jiajun Xu, Qiujin Guo, Xiaoying Ma, Jun Xu
  • Publication number: 20240121798
    Abstract: Systems, methods and devices for control channel monitoring may include a wireless communication device receiving, from a wireless communication node, a plurality of parameters. The wireless communication device may perform, responsive to a trigger event, a PDCCH monitoring behavior comprising at least one of PDCCH monitoring according to a search space set (SSS) group from N SSS groups or skipping of PDCCH monitoring according to a skipping period, based on the plurality of parameters. The parameter N may be an integer greater than or equal to two and less than or equal to ten. The skipping period may be determined from one or more candidate skipping periods.
    Type: Application
    Filed: July 14, 2023
    Publication date: April 11, 2024
    Applicant: ZTE Corporation
    Inventors: Qiujin GUO, Mengzhu CHEN, Jun XU, Xiaoying MA, Yuzhou HU, Xuan MA
  • Patent number: 11955448
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Jung Kyu Han, Hongxia Feng, Xiaoying Guo, Rahul N. Manepalli
  • Publication number: 20240112971
    Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
  • Patent number: 11948898
    Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Hongxia Feng, Xiaoying Guo, Benjamin T. Duong
  • Patent number: 11950186
    Abstract: Techniques are described to enable a user equipment (UE) to save power consumption and/or can enable the UE to acquire the channel state in time without reducing the UE's data transmission efficiency. An example technique includes determining, by the communication device, an operating mode based on a first signaling, and operating the communication device in the operating mode, where the operating mode includes any one of a normal mode, a first power saving mode, a second power saving mode, a third power saving mode, or a fourth power saving mode.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 2, 2024
    Assignee: ZTE Corporation
    Inventors: Xiaoying Ma, Jun Xu, Mengzhu Chen, Hao Wu, Qiujin Guo, Xuan Ma, Focai Peng
  • Publication number: 20240105575
    Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Jason M. GAMBA, Haifa HARIRI, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Hiroki TANAKA, Kyle MCELHINNY, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Haobo CHEN, Bai NIE, Numair AHMED
  • Publication number: 20240105576
    Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core and a pad over the core. In an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. In an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Kyle MCELHINNY, Xiaoying GUO, Hiroki TANAKA, Haobo CHEN
  • Patent number: 11942334
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Kristof Kuwawi Darmawikarta, Vahidreza Parichehreh, Veronica Aleman Strong, Xiaoying Guo
  • Publication number: 20240098697
    Abstract: This disclosure relates generally to a method, device, and system for transmitting and receiving paging indication in wireless communications. One method performed by a UE n an idle or an inactive state including receiving a Downlink Control Information (DCI) from a wireless communication node, wherein the DCI is scramble by a Radio Network Temporary Identification (RNTI) and comprises a paging indication, and wherein the paging indication indicates whether the UE is to receive a next coming paging occasion; resolving the paging indication from the DCI in response to determining that a predetermined condition is met; and determining whether the UE is to receive the next coming paging occasion based on the paging indication.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: ZTE Corporation
    Inventors: Focai PENG, Mengzhu CHEN, Jun XU, Xuan MA, Qiujin GUO, Xiaoying MA
  • Publication number: 20240083852
    Abstract: The present application relates to a synthesis method for N-methyl-3-substituted methyl-4-pyrazolamide derivative and N-methyl-3-substituted methyl-4-pyrazolic acid, including the following steps: step S1: synthesis of intermediate E; step S2: synthesis of intermediate D; step S3: synthesis of intermediate C; step S4: synthesis of N-methyl-3-substituted methyl-4-pyrazolamide derivative; and synthesis of N-methyl-3- substituted methyl-4-pyrazolic acid by decomposition of N-methyl-3-substituted methyl-4-pyrazolamide derivative.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 14, 2024
    Inventors: Shengxue LIU, Yintao SHI, Qiang GONG, Sufang ZHONG, Jianjiang ZHANG, Xiaoyuan QIAN, Fang GUO, Rujun CHEN, Xiaoying JIAN
  • Publication number: 20240071848
    Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Bohan SHAN, Haobo CHEN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Bai NIE, Gang DUAN, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying David XU, Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD
  • Patent number: 11881182
    Abstract: Aa light-emitting device driver chip, a backlight module, and a display panel are provided. The light-emitting device driver chip includes at least two current control circuits and a parallel control circuit. Each of the at least two current control circuits includes a current control module. A control output node of the current control module is electrically connected to a corresponding one of the output ports. The parallel control circuit is electrically connected between the at least two current control circuits and is configured to control, according to a parallel control signal received from a first input port, the current control modules of the at least two current control circuits to be electrically connected to enable the current control modules of the at least two current control circuits to output the same current to corresponding ones of the output ports through the control output nodes.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: January 23, 2024
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaoying Guo
  • Publication number: 20240005881
    Abstract: Aa light-emitting device driver chip, a backlight module, and a display panel are provided. The light-emitting device driver chip includes at least two current control circuits and a parallel control circuit. Each of the at least two current control circuits includes a current control module. A control output node of the current control module is electrically connected to a corresponding one of the output ports. The parallel control circuit is electrically connected between the at least two current control circuits and is configured to control, according to a parallel control signal received from a first input port, the current control modules of the at least two current control circuits to be electrically connected to enable the current control modules of the at least two current control circuits to output the same current to corresponding ones of the output ports through the control output nodes.
    Type: Application
    Filed: August 29, 2022
    Publication date: January 4, 2024
    Applicant: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaoying GUO
  • Publication number: 20240006285
    Abstract: Substrate assemblies having adhesion promotor layers and related methods are disclosed. An example apparatus includes a substrate, a dielectric layer, a first copper layer between the substrate and the dielectric layer, and a film between the dielectric layer and the first copper layer. The film including silicon and nitrogen and being substantially free of hydrogen. A via in the dielectric layer is to provide access to the first copper layer. A portion of the first copper layer uncovered in the via, a wall of the via and the portion of the first copper layer to be substantially free of fluorine. A seed copper layer positioned on the dielectric layer. The via wall and the portion of the first copper layer. The seed copper layer and the first copper layer define an undercut at an interface between the seed copper layer and the first copper layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Yi Yang, Suddhasattwa Nad, Xiaoying Guo, Jieying Kong, Ala Omer, Christy Sennavongsa, Wei Wei, Ao Wang
  • Publication number: 20230408044
    Abstract: The present disclosure discloses a flammable and explosive liquid transportation system and a method and an application thereof. The system includes a gas inlet pipe and a liquid transportation pipeline; a first valve and a second valve are sequentially disposed on the gas inlet pipe; two ends of the liquid transportation pipeline respectively communicate with the raw material barrel and a reaction vessel, a third valve, a fifth valve, and a seventh valve are sequentially disposed on the liquid transportation pipeline; the gas inlet pipe and the liquid transportation pipeline communicate with each other, and a fourth valve is disposed on the connecting pipe; a bypass pipe is disposed on the liquid transportation pipeline, and a sixth valve is disposed on the bypass pipe. The present disclosure resolves problems of a high risk and poor environmental protection caused by an existing flammable and explosive liquid transfer manner.
    Type: Application
    Filed: April 2, 2022
    Publication date: December 21, 2023
    Inventors: Bo LI, Sichuan LIU, Wenjun LIU, Changbin WANG, Hongbo TAN, Xiaoying GUO, Liang WANG
  • Publication number: 20230317024
    Abstract: The present application discloses a backlight module and a display device. The backlight module includes a plurality of light-emitting units, a plurality of drive chips, a plurality of cascaded voltage comparators, and a voltage adjustment module. The light-emitting unit connected to a control terminal of a same drive chip is connected with a same initial drive voltage. The plurality of cascaded voltage comparators output an adjustment voltage in a N-th stage based on a preset voltage and a plurality of to-be-detected voltages. The voltage adjustment module is configured to adjust the initial drive voltage based on the adjustment voltage in the N-th stage.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 5, 2023
    Inventors: Xiaoying GUO, Junyao FAN
  • Patent number: 11769735
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo