Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.

Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.

Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.

Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.

Abstract: Methods, systems, apparatus, and articles of manufacture to cool integrated circuit packages having glass substrates are disclosed. An example glass core of an integrated circuit (IC) package disclosed herein includes a fluid inlet to receive a cooling fluid, a fluid outlet, and a channel to fluidly couple the fluid inlet to the fluid outlet, the cooling fluid to flow through the channel from the fluid inlet to the fluid outlet, the channel fluidly isolated from one or more vias extending between a first surface and a second surface of the glass core.

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.

Abstract: An electronic system includes a substrate that includes a glass core layer including a cavity formed through the glass core layer; at least one active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer and a first surface of the at least one active component die, wherein the first buildup layer includes electrically conductive interconnect contacting the at least one active component die and extending to a first surface of the substrate; a second buildup layer contacting a second surface of the glass core layer and a second surface of the at least one active component die; and one or more solder bumps on a second surface of the substrate and contacting the second surface of the at least one active component die.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.

Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus. The metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.

Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core and a pad over the core. In an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. In an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.

Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.