Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.

Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.

Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate, and a first pad over the package substrate. In an embodiment, a layer is over the package substrate, where the layer is an insulating material. In an embodiment, the electronic package further comprises a via through the layer and in contact with the first pad. In an embodiment a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width. In an embodiment, the electronic package further comprises a second pad over the via.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: A terminal device may include: a housing; a first radiator disposed in the housing and configured to receive and transmit wireless signals; and a conducting layer disposed on an inner surface of a back shell of the housing and coupled with the first radiator to form a second radiator which is configured to receive and transmit the wireless signals.

Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

Abstract: Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: A terminal device may include: a housing; a first radiator disposed in the housing and configured to receive and transmit wireless signals; and a conducting layer disposed on an inner surface of a back shell of the housing and coupled with the first radiator to form a second radiator which is configured to receive and transmit the wireless signals.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: In some examples, iterative sampling based dataset clustering may include sampling a dataset that includes a plurality of items to identify a specified number of sampled items. The sampled items may be clustered to generate a plurality of clusters. Un-sampled items may be assigned from the plurality of items to the clusters. Remaining un-sampled items that are not assigned to the clusters may be identified. A ratio associated with the remaining un-sampled items and the plurality of items may be compared to a specified threshold. Based on a determination that the ratio is greater than the specified threshold, an indication of completion of clustering of the plurality of items may be generated.

Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a plurality of conductive layers over a package substrate. The conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate. The semiconductor package also includes a solder resist that surrounds the FLIs, where the solder resist has a top surface that is substantially coplanar to top surfaces of the FLIs, a bridge coupled directly to the first conductive layer with solder balls, where the first conductive layer is coupled to the FLIs, and a dielectric over the conductive layers, the bridge, and the solder resist of the package substrate. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first conductive layer may include first conductive pads and second conductive pads. The FLIs may include first conductive vias, second conductive vias, diffusion layers, and third conductive pads.

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. Forming a first solder resist (SR) layer on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. Forming a second solder resist (SR) layer on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.