Patents by Inventor Xiaoying (Janet) He

Xiaoying (Janet) He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12035279
    Abstract: The present disclosure describes methods, system, and devices for determining a location of paging early indication (PEI). One method includes receiving, by a user equipment (UE), configuration information of a paging early indication occasion (PEI-O), wherein the configuration information comprises a frame-level offset list and a symbol-level offset list, the frame-level offset list comprises one or more frame-level offset, and the symbol-level offset list comprises one or more symbol-level offset; and detecting, by the UE, a paging early indication (PEI) in the PEI-O, wherein the PEI-O is determined by a frame-level offset from a start of a first paging frame (PF) of at least one PF associated with the PEI-O to a reference point and a symbol-level offset from the reference point to a start of a first physical downlink control channel (PDCCH) monitor occasion of the PEI-O.
    Type: Grant
    Filed: March 11, 2024
    Date of Patent: July 9, 2024
    Assignee: ZTE CORPORATION
    Inventors: Xuan Ma, Mengzhu Chen, Jun Xu, Focai Peng, Xiaoying Ma
  • Patent number: 12035324
    Abstract: This application provides a data sending method, a data sending apparatus, and a terminal device, to improve utilization of a configured grant resource. The method includes: A terminal device receives a configuration message from a network device. The configuration message is used to indicate a configured grant, and the configuration message includes information about a timer corresponding to the configured grant. The terminal device determines that the configured grant is used for a HARQ process, and starts the timer for the HARQ process. To-be-sent data in the HARQ process is data on a first logical channel. During running of the timer, when there is to-be-newly-transmitted data on a second logical channel, the timer stops running, or a running state of the timer is ignored. The data on the second logical channel is sent by using the configured grant.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 9, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaoying Xu, Qufang Huang, Chong Lou, Qinghai Zeng, Tao Cai
  • Publication number: 20240222238
    Abstract: An integrated circuit device substrate includes a glass substrate with a first major surface comprising a plateau region, a cavity region, and a wall between the plateau region and the cavity region. The first major surface includes thereon a first dielectric region, and the plateau region includes a plurality of conductive pillars. A second major surface of the glass substrate opposite the first major surface includes thereon a second dielectric layer, wherein the second dielectric layer includes at least one dielectric-free window underlying the cavity region.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Bai Nie, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
  • Publication number: 20240222210
    Abstract: An integrated circuit device substrate includes a first glass layer, a second glass layer, and a dielectric interface layer between the first glass layer and the second glass layer. A plurality of conductive pillars extend through the first glass layer, the dielectric layer and the second glass layer, wherein the conductive pillars taper from a first diameter in the dielectric layer to a second diameter in the first glass layer and the second glass layer, and wherein the first diameter is greater than the second diameter.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240218625
    Abstract: The present disclosure relates to a rotating construction platform based on a monopile, including a rotary connecting mechanism set on the top of the monopile and a working platform set on the rotary connecting mechanism. The rotary connecting mechanism includes an upper connecting tube, a lower connecting tube and a rotary support structure located between the upper connecting tube and the lower connecting tube. The working platform is fixedly connected to the upper connecting tube, and the lower connecting tube is detachably fixed to the top of the monopile. At least one side of the working platform sticks out of the side of the monopile. The rotating construction platform of the present disclosure can improve the continuity of construction operations, save construction time and costs, avoid vessel machinery from hitting monopile, improve construction positioning accuracy and ensure construction quality.
    Type: Application
    Filed: August 20, 2021
    Publication date: July 4, 2024
    Applicants: Shanghai Investigation, Design & Research Institute Co., Ltd., HuaNeng Jiangsu Clean Energy Branch
    Inventors: Zeyang LYU, Dongzhen WANG, Juan JIANG, Zhenghua YANG, Xiaolu CHEN, Zhaofeng HANG, Chunyu GUAN, Lihua YANG, Zhongyuan YAO, Yang HUA, Xiaoying CAI, Mingjiang LIU, Yu ZHANG, Qihui YAN
  • Publication number: 20240224458
    Abstract: A side rack includes a chassis, a first horizontal support coupled to the chassis, a second horizontal support coupled to the chassis, and a third horizontal support coupled to the chassis. The first horizontal support is configured to be coupled to a first piece of equipment, the second horizontal support is configured to be coupled to the first piece of equipment, and the third horizontal support is configured to be coupled to a second piece of equipment.
    Type: Application
    Filed: December 4, 2023
    Publication date: July 4, 2024
    Inventors: Trevor William Norton, Fu Zhou, Jie Zhu, Xiaoying Zeng, Hao Lu
  • Publication number: 20240222283
    Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Hongxia Feng, Bohan Shan, Bai Nie, Xiaoxuan Sun, Holly Sawyer, Tarek Ibrahim, Adwait Telang, Dingying Xu, Leonel Arana, Xiaoying Guo, Ashay Dani, Sairam Agraharam, Haobo Chen, Srinivas Pietambaram, Gang Duan
  • Publication number: 20240222243
    Abstract: An integrated circuit device substrate includes a first glass layer with a redistribution layer mounting region and an integrated circuit device mounting region, wherein a first major surface of the first glass layer is overlain by a first dielectric layer, and wherein the first glass layer includes a first plurality of conductive pillars. A second glass layer is on the redistribution layer mounting region on the first glass layer, wherein the second glass layer includes a second dielectric layer on a second major surface thereof, and wherein the second dielectric layer is bonded to the first dielectric layer on the first major surface of the first glass layer, the second glass layer including a second plurality of conductive pillars electrically interconnected with the first plurality of conductive pillars in the first glass layer.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Kyle Jordan Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240222257
    Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
  • Publication number: 20240219655
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Bai Nie, Brandon C. Marin, Dingying Xu, Gang Duan, Hongxia Feng, Jeremy D. Ecton, Kristof Darmawikarta, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Xiaoying Guo, Yiqun Bai, Ziyin Lin
  • Publication number: 20240222345
    Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Bai Nie, Srinivas Pietambaram, Gang Duan, Kyle Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20240222304
    Abstract: Methods and apparatus to reduce solder bump bridging between two substrates. An apparatus includes a first substrate including a first bump and a second bump spaced apart from the first bump, the first bump including a first base, the second bump including a second base; and a second substrate including a third bump and a fourth bump spaced apart from the third bump, the third bump including a third base, the fourth bump including a fourth base, the first base electrically coupled to the third base by first solder, the second base electrically coupled to the fourth base by second solder, the first solder having a first volume, the second solder having a second volume, the first volume less than the second volume.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Jiaqi Wu, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
  • Publication number: 20240222301
    Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Dingying Xu, Sairam Agraharam, Ashay Dani, Eric J. M. Moret, Tarek Ibrahim
  • Publication number: 20240219195
    Abstract: The disclosure provides a system, a method, and a computer program product for optimization of lane data. The system may be configured to categorize each location of a set of locations included in the lane data of each lane marking of the plurality of lane markings, into at least one of: a first area or a second area of a topological area. The system may further determine the lane data of each lane marking to be in at least one of: a first group, a second group or a third group, based on each categorized location of the set of locations. The system may further process the lane data associated with each lane marking of the plurality of lane markings based on the determined first group, the second group or the third group.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Zhenhua ZHANG, Xiaoying JIN
  • Publication number: 20240219660
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Yiqun Bai, Dingying Xu, Eric J.M. Moret, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Bin Mu
  • Publication number: 20240223434
    Abstract: Techniques are described for detecting that a client device physically connected to a network device is “stuck,” that is, the client device is not sending or receiving network packets with the network device. A network management system (NMS) receives current network statistics of ports of network devices with respect to client devices physically connected to the ports. The NMS identifies a candidate client device connected to a particular port of a particular network device for which the current network statistics indicate an issue. The NMS detects anomalous behavior of the candidate client device based on one or more features of the current network statistics, historical baseline statistics associated with the candidate client device, and peer statistics associated with one or more peer client devices of a same device type as the candidate client device. The NMS outputs a notification of the anomalous behavior.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Jing Cheng, Abhiram Madhugiri Shamsundar, Pawan Gandhi, Xiaoying Wu, Jisheng Wang
  • Publication number: 20240223489
    Abstract: The disclosure describes one or more techniques for performing automated scheduling and/or orchestration of synthetic tests for network sites. For example, a network management system comprises a memory and one or more processors in communication with the memory and configured to: determine, based on data received from a plurality of network devices of a network, a network condition to perform a test, wherein the network condition comprises one or more of a time window to perform the test or one or more network devices of the plurality of network devices to perform the test; instruct, based on the network condition, the one or more network devices to perform the test; identify, based on data obtained from the one or more network devices that performed the test, an issue of the network; and perform an action based on the identified issue.
    Type: Application
    Filed: December 22, 2023
    Publication date: July 4, 2024
    Inventors: Xiaoying Wu, Jacob Thomas, Wesley Purvis, Gorakhanath Kathare, Gurpreet Singh, Rinoob Babu, Prathamesh Dnyanesh Kumkar, Huan Thien Vu, Aftab Ahmed Shaikh
  • Publication number: 20240222259
    Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Haobo Chen, Bohan Shan, Xiyu Hu, Rhonda Jack, Catherine Mau, Hongxia Feng, Xiao Liu, Wei Wei, Srinivas Pietambaram, Gang Duan, Xiaoying Guo, Dingying Xu, Kyle Arrington, Ziyin Lin, Hiroki Tanaka, Leonel Arana
  • Publication number: 20240222136
    Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ashay A. Dani, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Wei Wei, Ziyin Lin
  • Publication number: 20240220389
    Abstract: Techniques are disclosed for a network management system (NMS) that performs quality of service (QOS) monitoring and troubleshooting of user experience issues occurring outside of a network managed by the NMS using data obtained from third-party sources. For example, an NMS obtains third-party data of a third-party application server or third-party service provider server from a third-party monitoring vendor. The NMS identifies a user experience issue indicated by the third-party data and stitches the third-party data to network data received from network devices. The NMS determines a root cause or a remedial action of the user experience issue based at least on the network data received from the one or more network devices. The NMS generates a notification for presentation to an administrator device which identifies the root cause or the remedial action of the user experience issue.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Inventors: Xiaoying Wu, Jisheng Wang, Prashant Kumar, Pawan Gandhi