Abstract: A output driver architecture (100) is proposed that uses thin gate-oxide core and thin gate-oxide Drain-extended transistors that can directly interface with voltage supplies up to six times the normal rating of the transistor. A bias generator (101), level shifter (103) and output stage (105) are adapted to buffer an input signal with a voltage swing of less than the normal operating voltage of the transistors to an output signal with a voltage swing of up to approximately six times the normal operating voltage of the transistors. The bias generator is interfaced directly with a high voltage power supply and generates a bias voltage with a magnitude of less than the dielectric breakdown of the transistors internal to the level shifter and output stage.

Abstract: An LDO regulator automatically switches from the SLEEP mode to the ON mode without the need for an externally generated control signal. The LDO regulator utilizes a pair of drive amplifiers to drive a SLEEP mode pass transistor and a normal ON mode pass transistor, respectively. The regulator also has a circuit for adjusting the bias applied to the amplifiers for each mode of operation.

Abstract: A Miller compensated voltage regulator, adapted to be supplied with power from a voltage supply, and having an input port and an output port. The voltage regulator includes a voltage regulation circuit responsive to a reference voltage at the input port to provide a regulated voltage at the output port. The voltage regulation circuit includes a first amplifier adapted to receive a reference voltage at a first input, having a second input, and having an output, and also a second amplifier having a first input coupled to an internal node, the internal node being coupled to the output of the first amplifier, the second amplifier having a second input adapted to receive a bias voltage and having an output. A pass transistor is provided having a source coupled to the voltage supply, having a drain coupled to the output port, and having a gate coupled to the output of the second amplifier, and a Miller compensation capacitor is provided coupled between the output port and the internal node.

Abstract: The present invention provides a low drop-out voltage regulator (200) that reduces gate capacitance and simplifies the compensation needed to maintain stability, without requiring additional and/or larger Miller capacitors (108), by splitting the output (220, 221) of the driver (112A) for different operational modes, selectively driving a small power device (206), a large power device (214) or both based on the mode.

Abstract: The low dropout voltage regulator (LDO) circuit with improved power supply rejection ratio includes: a first amplifier 20 having a first input coupled to a reference voltage node Vref; a second amplifier 22 having an input coupled to an output of the first amplifier 20; a pass transistor 24 having a control node coupled to an output of the second amplifier 22; a feedback circuit 26 and 28 having an input coupled to the pass transistor 24 and an output coupled to a second input of the first amplifier 20; an inverting gain stage 36 coupled to the input of the second amplifier 22; and a high pass filter 42, 44, and 38 coupled between a power supply node and a control node of the inverting gain stage 36. The circuit uses the high pass filter 42, 44, and 38 and inverting gain stage 36 to feedforward the power supply ripple into the LDO's control loop which counter-acts the impact of the supply ripple on the output node Vo.

Abstract: A low dropout voltage regulator includes: a first amplifier A1 having a reference voltage node VREF coupled to a first input; a second amplifier A2 having an input coupled to an output of the first amplifier A1; a variable bias current source I1 coupled to the first amplifier A1 and having a control node coupled to an output of the second amplifier A2; a power switch M1 having a control node coupled to the output of the second amplifier A2 and having a first end coupled to a source voltage node VDD; and a feedback circuit R1 and R2 having an input coupled to a second end of the power switch M1 and an output coupled to a second input of the first amplifier A1. The best node in the system that detects the load current level is the output of the second amplifier A2. This signal is used to modulate the bias current I1 of the first amplifier A1 by increasing the bias current when the load current increases and vice versa, which consequently modulates the transconductance of amplifier A1.

Abstract: A folded-cascode amplifier (30) having a small signal gm being boosted and transferred from the input stage to the output stage to reduce current consumption and expand bandwidth. The amplifier has a pair of second amplifiers (A) operating as boosting amplifiers that provide a pole at its output node, which is at a fairly low frequency. A compensation scheme is employed to introduce a zero to cancel out this pole, and as a side benefit, another zero is brought in which is used to cancel out a second pole of the original folded-cascode amplifier so that bandwidth is actually expanded. Two compensation capacitors (C1, C2) serve two purposes, one, providing a dominant pole to the main amplifier due to a Miller Effect, where the value of the two capacitors are much smaller than for conventional folded-cascode amplifiers, and two, introduce two zeros which cancel out two high frequency poles so that bandwidth is expanded.

Abstract: A high power supply ripple rejection (PSRR) internally compensated low drop-out voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator. The non-inversion variable gain amplifier is further operational to adjust its gain in response to a load current passing through the power PMOS device such that as the load current increases, the gain decreases, wherein the voltage regulator unity gain bandwidth associated with the loop formed by the compensation capacitor is kept substantially constant.

Abstract: A high-speed parallel-to-serial CMOS data transmitter uses a D Flip-flop matrix architecture to combine a shift scheme with a selection scheme to serialize parallel bit data. Data is partially serialized through multi data paths at a much lower frequency and a time-division multiplex scheme selects one bit from each data path allowing for pipelined data processing. The CMOS architecture uses selective load clock mode switching allowing different word bit widths to be processed simply by adjusting the frequency of a loading clock.