Abstract: A system includes a voltage booster circuit to receive an input voltage and provide an output voltage. A first device that is coupled to the voltage booster circuit to receive a digitized input voltage and a digitized output voltage and to determine, based on the digitized input voltage and the digitized output voltage, a first threshold level for the voltage booster circuit to operate in a pulse frequency modulation (PFM) mode. A second device that is coupled to the voltage booster circuit to receive the input voltage and the output voltage and to determine a second threshold level for the voltage booster circuit to operate in the PFM mode. A selector device that is coupled to the first device and the second device to select one of the first threshold level or the second threshold level for the voltage booster circuit.

Abstract: A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

Abstract: An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

Abstract: An apparatus includes a first circuit that has a photodetector. The photodetector is reverse-biased by a reverse-bias voltage. A common mode voltage is added to the reverse-bias voltage to provide an offset to the photodetector voltage. A second circuit is coupled to the first circuit to provide the common mode voltage for the first circuit. A third circuit is coupled to the second circuit that includes a first voltage source and a second voltage source having opposite voltages equal to half of the reverse-bias voltage. Each one of the first voltage source and the second voltage source are coupled between separate input and output nodes of input and output ports of the third circuit. The first voltage source and the second voltage source provide the reverse-bias voltage to the first circuit to reverse-bias the photodetector. The third circuit provides a photodetector current at an output of the third circuit.

Abstract: An apparatus for detecting optical signals includes a photodetector. The photodetector is reverse-biased by a first voltage and a second voltage is added to the first voltage to provide an offset equal to the second voltage for the photodetector. A first circuit is coupled to the first circuit to provide the second voltage for the photodetector and a second circuit is coupled to the first circuit to provide the first voltage to the photodetector to reverse-bias the photodetector. The second circuit provides an output voltage proportional to a current of the photodetector at an output of the second circuit.

Abstract: An apparatus includes a circuitry to perform a first startup stage and to vary, during a second startup stage subsequent to the first startup stage, a duty cycle of a pulse controlling one or more switches of the circuitry.

Abstract: A device includes a first circuit, a ground, a reference voltage source that provides a reference voltage, and a first transistor that includes a first drain, a first source, and a first gate. The first circuit is coupled between the first source and the ground. The device has a second transistor that includes a second source and a second gate. The second transistor is biased as a source follower with the second source of the second transistor being set at the reference voltage. The first gate of the first transistor is coupled to the second gate of the second transistor, the first source has equal voltage as the second source, and the first circuit is coupled between the first source having the reference voltage and the ground to draw a constant current from the first source and to bias the first transistor in the saturation region to reduce parasitic capacitance.

Abstract: An apparatus of the subject technology includes a first comparator circuit having a first offset voltage and a first circuit to generate a first code based on the first offset voltage. The apparatus further comprises a second comparator circuit having a second offset voltage and a second circuit that generates a second code based on the second offset voltage and the first code. The first offset voltage and the second offset voltage are partially compensated based on the second code.

Abstract: An apparatus includes a boost converter including a compensation circuit to implement a switching scheme and partitioned into multiple circuits and a calculator circuit configured to determine a voltage to be applied to the compensation circuit. The multiple circuits each includes a capacitor and a voltage is applicable to pre-charge the capacitors to a voltage corresponding to an error voltage, as determined by the calculator circuit. The pre-charged capacitors can enable an immediate settling of the error voltage to achieve an instantaneous response of the compensation circuit. Beneficially, the apparatus can drive a power stage circuit to supply power to a load (e.g., LED) without overshoot or undershoot.

Abstract: A circuit includes a boost circuit, a first circuit coupled to the boost circuit and a second circuit coupled to the boost circuit. The boost circuit, the first circuit, and the second circuit form an open loop. The first circuit and the second circuit maintain a switching frequency of the boost circuit above a threshold frequency.

Abstract: An apparatus includes a switched-capacitor resistor that provides an equivalent resistance that can be used as a reference resistor. The switched-capacitor resistor includes a capacitor and a pair of switches that alternately switch (e.g., open and close) in order to charge and discharge the capacitor. The switching frequency of the switches can be controlled by a clock phase generator that generates non-overlapping pulses. To further control the frequency, a frequency locked loop circuit can also be used.

Abstract: An apparatus of the subject technology includes a circuit to switch a first current based on a switching frequency and generate an output voltage, and a first circuit coupled to the circuit to adjust the switching frequency through changing a frequency of the circuit to a value higher than a threshold.

Abstract: An apparatus includes a temperature sensing circuit that includes both on-chip and off-chip components. The apparatus includes components that use the same source as a reference voltage, thus allowing variations in the reference voltage to be compensated for. Additionally, the apparatus can provide error averaging to compensate for deterministic error sources.

Abstract: A device (e.g., SAR ADC device) include a DAC circuit and generates a digital output based on logic circuitry that includes SAR logic. Additional logic circuitry includes delta modulation circuitry and dynamic element matching circuitry. The delta modulation circuitry provides several digital outputs of the SAR DAC, while the dynamic element matching circuitry selects a different set of capacitors from the DAC circuit. Each cycle is added together and averaged, and then added to the digital output from the SAR logic.

Abstract: A system includes a voltage booster circuit to receive an input voltage and provide an output voltage. A first device that is coupled to the voltage booster circuit to receive a digitized input voltage and a digitized output voltage and to determine, based on the digitized input voltage and the digitized output voltage, a first threshold level for the voltage booster circuit to operate in a pulse frequency modulation (PFM) mode. A second device that is coupled to the voltage booster circuit to receive the input voltage and the output voltage and to determine a second threshold level for the voltage booster circuit to operate in the PFM mode. A selector device that is coupled to the first device and the second device to select one of the first threshold level or the second threshold level for the voltage booster circuit.

Abstract: An apparatus of the subject technology includes a circuit consisting of an inductor and a switch to allow a current to flow through the inductor and charge a capacitor of the circuit. A first circuit is coupled to the circuit and is used to simulate an event. A second circuit sets a threshold for triggering the event, while partially compensating a propagation delay.

Abstract: A controller includes a first circuit that receives first and second input signals and generates an output pulse based on the first and second input signals. A timer circuit of the controller generates the first input signal for the first circuit. A second circuit of the controller generates the second input signal for the first circuit. In response to the second input signal being set to a first value, smaller than a second value, the first circuit sets the output pulse to the second value and start a first duration. In response to the second input signal being set to the second value and the first input signal changing from the first value to the second value, the first circuit sets the output pulse to the first value to end the first duration and start a second duration such that the second duration is maintained more than a time limit.

Abstract: An apparatus includes a digital ramp generator comprising a delay line, the delay line comprising one or more delay elements and an oscillator, wherein the digital ramp generator is configured to generate a code based on respective outputs of the one or more delay elements, a digital to analog converter coupled to the digital ramp generator, wherein the digital to analog converter is configured to generate a reference signal, wherein the reference signal is generated based, at least in part, on the code, and a driver coupled to the digital to analog converter, the driver configured to generate a drive current based, at least in part, on the reference signal.

Abstract: A circuit includes first and second power devices that include first and second field effect transistors (FET). A first channel is located between a first drain and a first source of first FET and a second channel is located between a second drain and a second source of second FET. First and second drains are coupled to first common junction and first and second sources are coupled to second common junction. The first common junction is configured to receive a current. A switch controller is coupled to a first gate of the first FET and to a second gate of the second FET to apply a bias voltage to the first and second gates one by one and in turn. An analog to digital converter coupled to first common junction and second common junction and configured to alternately digitize a voltage of the first channel or the second channel.

Abstract: An envelope tracking device includes circuitry that senses a current of an input state of the envelope tracking device. The circuitry also senses an output voltage of the envelope tracking device, and turns on at least one of a first and a second output switches to generate an output current based on at least one of the sensed current and the sensed voltage.