Abstract: An envelope tracking device includes circuitry that senses a current of an input state of the envelope tracking device. The circuitry also senses an output voltage of the envelope tracking device, and turns on at least one of a first and a second output switches to generate an output current based on at least one of the sensed current and the sensed voltage.

Abstract: A device, a circuit, and a method for current bypass are provided. The device includes circuitry detects an overload condition at a switching regulator output, enables a current bypass path including a linear current source in response to detecting the overload condition, and digitizes a difference between a load current and a switching regulator output current. The linear current source generates an active current assist signal based on the digitized difference between the load current and the switching regulator output current.

Abstract: A device, a circuit, and a method for current bypass are provided. The device includes circuitry detects an overload condition at a switching regulator output, enables a current bypass path including a linear current source in response to detecting the overload condition, and digitizes a difference between a load current and a switching regulator output current. The linear current source generates an active current assist signal based on the digitized difference between the load current and the switching regulator output current.

Abstract: An envelope tracking device includes circuitry that senses a current of an input state of the envelope tracking device. The circuitry also senses an output voltage of the envelope tracking device, and turns on at least one of a first and a second output switches to generate an output current based on at least one of the sensed current and the sensed voltage.

Abstract: A sensor interface includes on-chip relaxation oscillator circuit and a PLL that operate cooperatively to generate a highly accurate clock signal on-chip using low-power components. A photodiode generates a current signal based on an optical signal that is representative of a sensor signal. An ADC that operates based on the highly accurate clock signal generates a digital signal based on the current signal generated by the photodiode, and a processor processed the digital signal to estimate sensor data within the sensor signal. Examples of characteristics that may be sensed can include environmental characteristics (e.g., temperature, humidity, barometric pressure, etc.) and/or biomedical characteristics (e.g., body temperature, heart rate, respiratory rate, blood pressure, etc.). If desired, an amplifier processes the photodiode-provided current signal before it is provided to the ADC. Also, one or more CDACs that generate feedback currents may be used to reduce noise sensitivity of the sensor interface.

Abstract: Systems, apparatuses, and methods provided for ping-pong charge pumps. Flying capacitors present in ping-pong charge pumps are operated out of phase to increase equalization periods. Out-of-phase operation also decreases voltage differences between flying capacitors during equalization periods thus decreasing ping-pong charge pump output voltage ripple and snapback. The voltages of the flying capacitors may be equalized without the use of an equalization switch. Differential control currents that are based on the voltage difference between the flying capacitors are used to enable or disable the flying capacitors from driving an output load of the ping-pong charge pump during certain phases of operation. A capacitor with a lower voltage may be disabled, thus providing for voltage equalization as the enabled capacitor sources current to the output load. The flying capacitors are also equalized during overlapping time periods in which the flying capacitors are charging.

Abstract: A CMOS analog and audio front-end circuit includes an enhanced analog-to-digital converter (ADC) that achieves a desired signal-to-noise-and-distortion (SNDR) and an analog-front-end transmit (TX) digital-to-analog converter (DAC). The enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop and can substantially reduce signal transfer function (STF) peaking of the enhanced ADC. The CMOS analog and audio front-end circuit is integrated with a baseband processor.

Abstract: Presented are circuits and methods for providing real-time short-circuit detection, capable of detecting a short-circuit prior to occurrence of an over-limit current event. Such a circuit can be used to provide real-time short-circuit detection for a switched-mode system for a switched-mode system having a pre-driver and a power stage, and includes a reference block for generating a reference voltage according to drive signals provided by the pre-driver, and a comparator, which may be a synchronized comparator. The comparator is configured to compare the reference voltage to a switching node voltage generated in a power stage of the switched-mode system, and to produce an output enabling detection of the short-circuit in the switched-mode system.

Abstract: Systems and methods for managing current consumption by an electronic device are provided. The electronic device includes first and second clock units. The first clock unit generates a first reference clock signal based on a first current input. The second clock unit generates a second reference clock signal based on a second current input greater than the first current input. The system includes a control module configured to identify an application to be executed. The control module is configured to determine whether the application is associated with a first current consumption level or a second current consumption level greater than the first current consumption level. The control module is configured to select the first or second reference clock signal based on whether the application is determined to be associated with the first or second current consumption level. The system includes circuitry configured to execute the application based on the selection.

Abstract: Methods, systems, and apparatuses for detecting and suppressing analog error in an output stage of a digital class-D amplifier are described. In embodiments, the digital class-D amplifier includes a PWM stage, an output stage, and a feedback circuit. The PWM stage receives the signal difference between an input digital signal and a feedback digital signal, generates a digital pulse-width modulated (PWM) signal based thereon, and provides the digital PWM signal as a first component of the digital feedback signal. The output stage receives the digital PWM signal and generates an analog output signal for driving a load responsive to the digital PWM signal. The feedback circuit combines an analog representation of the PWM signal and the analog output signal to generate a second component of the digital feedback signal.

Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.

Abstract: A circuit for a charge-pump low-dropout (LDO) regulator may include a comparator circuit configured to control a pass transistor based on an error signal. A pre-charge path may be provided between a supply voltage and an output node of the regulator. The pre-charge path may be configured to allow charging of an output capacitor to a pre-charge voltage during a pre-charge operation mode. The output capacitor may be coupled between the output node of the regulator and ground potential. The pass transistor may be configured to allow charging of the output capacitor during an LDO mode of operation. A charge-pump circuit may be configured to provide a current for charging the output capacitor during the LDO mode of operation.

Abstract: Systems and methods that reduce or remove idle tones and noise from an audio signal are provided. According to various embodiments, a level of the received input signal is detected and a control signal can be generated based on the detected level. When the detected level is above a pre-determined threshold value, then the input signal (which may have been processed) is output. When the input falls below the pre-determined threshold, then a constant signal is output instead, where the constant signal may be one of a ground signal, or other constant voltage signal.

Abstract: A CMOS analog and audio front-end circuit includes an enhanced analog-to-digital converter (ADC) that achieves a desired signal-to-noise-and-distortion (SNDR) and an analog-front-end transmit (TX) digital-to-analog converter (DAC). The enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop and can substantially reduce signal transfer function (STF) peaking of the enhanced ADC. The CMOS analog and audio front-end circuit is integrated with a baseband processor.

Abstract: Methods, systems, and apparatuses for detecting and suppressing analog error in an output stage of a digital class-D amplifier are described. In embodiments, the digital class-D amplifier includes a PWM stage, an output stage, and a feedback circuit. The PWM stage receives the signal difference between an input digital signal and a feedback digital signal, generates a digital pulse-width modulated (PWM) signal based thereon, and provides the digital PWM signal as a first component of the digital feedback signal. The output stage receives the digital PWM signal and generates an analog output signal for driving a load responsive to the digital PWM signal. The feedback circuit combines an analog representation of the PWM signal and the analog output signal to generate a second component of the digital feedback signal.

Abstract: Systems, apparatuses, and methods provided for ping-pong charge pumps. Flying capacitors present in ping-pong charge pumps are operated out of phase to increase equalization periods. Out-of-phase operation also decreases voltage differences between flying capacitors during equalization periods thus decreasing ping-pong charge pump output voltage ripple and snapback. The voltages of the flying capacitors may be equalized without the use of an equalization switch. Differential control currents that are based on the voltage difference between the flying capacitors are used to enable or disable the flying capacitors from driving an output load of the ping-pong charge pump during certain phases of operation. A capacitor with a lower voltage may be disabled, thus providing for voltage equalization as the enabled capacitor sources current to the output load. The flying capacitors are also equalized during overlapping time periods in which the flying capacitors are charging.

Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.

Abstract: A sensor interface includes on-chip relaxation oscillator circuit and a PLL that operate cooperatively to generate a highly accurate clock signal on-chip using low-power components. A photodiode generates a current signal based on an optical signal that is representative of a sensor signal. An ADC that operates based on the highly accurate clock signal generates a digital signal based on the current signal generated by the photodiode, and a processor processed the digital signal to estimate sensor data within the sensor signal. Examples of characteristics that may be sensed can include environmental characteristics (e.g., temperature, humidity, barometric pressure, etc.) and/or biomedical characteristics (e.g., body temperature, heart rate, respiratory rate, blood pressure, etc.). In desired, an amplifier processes the photodiode-provided current signal before it is provided to the ADC. Also, one or more CDACs that generate feedback currents may be used to reduce noise sensitivity of the sensor interface.

Abstract: A multi-mode line driver circuit designed to be fabricated in a CMOS process and capable of supporting a plurality of operating modes corresponding, for example, to different profiles of communication standards such as xDSL standards. The line driver circuit incorporates integrated mode switches with a two-stage amplifier architecture to relax amplifier requirements by distributing the signal gain into two amplifier stages. Reconfigurable feedback loops are provided to permit design optimization for particular modes of operation (e.g., ADSL and VDSL compliant modes). In one embodiment implemented as a Class-H amplifier, lift amplifier(s) are provided between a first amplifier stage and a second amplifier stage for controlling voltage supply levels of the second amplifier stage. The lift amplifiers may be enabled by voltage threshold detection circuitry that monitors either the input or the output signals of the first amplifier stage depending on the operable transmission mode.

Abstract: Systems and methods for managing current consumption by an electronic device are provided. The electronic device includes first and second clock units. The first clock unit generates a first reference clock signal based on a first current input. The second clock unit generates a second reference clock signal based on a second current input greater than the first current input. The system includes a control module configured to identify an application to be executed. The control module is configured to determine whether the application is associated with a first current consumption level or a second current consumption level greater than the first current consumption level. The control module is configured to select the first or second reference clock signal based on whether the application is determined to be associated with the first or second current consumption level. The system includes circuitry configured to execute the application based on the selection.