Patents by Inventor Xicheng Jiang
Xicheng Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6995594Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: May 28, 2004Date of Patent: February 7, 2006Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20050146819Abstract: An output stage protection system for protecting CMOS devices in an integrated circuit (IC) output stage during normal operations and power up/power down. In an embodiment, the output stage includes a pair of relatively low voltage CMOS devices coupled to a current source and IC core outputs. A first pair of relatively high voltage CMOS devices is coupled to the relatively low voltage pair and a biasing circuit. A second pair of relatively high voltage CMOS devices is coupled to a resistor, the first pair, and first and second output nodes, respectively. One or more diodes are coupled in series between the first and second output nodes and the resistor. In an embodiment, the output stage protection system protects CMOS devices in the output stage from electrostatic discharge (ESD). Input/output (I/O) pad ESD protection circuits are coupled to the I/O pads and include a clamp coupled to a local net.Type: ApplicationFiled: January 6, 2004Publication date: July 7, 2005Inventors: Xicheng Jiang, Ardie Venes
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Patent number: 6831584Abstract: An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches stores the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.Type: GrantFiled: August 22, 2003Date of Patent: December 14, 2004Assignee: Broadcom CorporationInventors: Xicheng Jiang, Zhengyu Wang, Frank Chang
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Publication number: 20040212416Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: May 28, 2004Publication date: October 28, 2004Applicant: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 6791388Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: January 17, 2003Date of Patent: September 14, 2004Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20040041721Abstract: An analog to digital converter includes an array of differential input amplifiers. Each amplifier inputs an input voltage and a corresponding voltage reference, and outputs a differential signal representing a comparison of the input voltage and the corresponding voltage reference. A plurality of latches stores the differential signal from each of the differential input amplifiers. A decoder converts the stored differential signals to N-bit digital output. A first interface amplifier is connected to a first edge amplifier of the array through a first cross point. A second interface amplifier is connected to a second edge amplifier of the array through a second cross point. The first interface amplifier and the second interface amplifier are connected to each other through a third cross point.Type: ApplicationFiled: August 22, 2003Publication date: March 4, 2004Applicant: Broadcom CorporationInventors: Xicheng Jiang, Zhengyu Wang, Frank Chang
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Publication number: 20030141914Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: January 17, 2003Publication date: July 31, 2003Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 6509773Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: GrantFiled: April 30, 2001Date of Patent: January 21, 2003Assignee: Broadcom CorporationInventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Jurgen Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020044618Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 18, 2002Inventors: Aaron W. Buchwald, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020044617Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 18, 2002Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020039395Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 4, 2002Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020039394Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.Type: ApplicationFiled: April 30, 2001Publication date: April 4, 2002Inventors: Aaron W. Buchwald, Myles Wakayama, Michael Le, Josephus Van Engelen, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Publication number: 20020034222Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discreet-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.Type: ApplicationFiled: April 30, 2001Publication date: March 21, 2002Inventors: Aaron Buchwald, Xicheng Jiang, Hui Wang, Howard A. Baumer, Avanindra Madisetti
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Patent number: 4908490Abstract: This invention is related to the process and apparatus for applying stressed skin sheet coverings to large passenger vehicles. The apparatus for the process, provided by this invention includes a single phase transformer, conductors, electric contactors and a guiding apparatus. The present invention uses a specialized transformer, capable of producing a strong electric current of low voltage as an energy source, utilizing the steel skin sheet as a resistor element in the output circuit, welding the steel sheet onto the frame while the steel sheet is heated by the electric current passing through the sheet, thereby elongating the sheet at a set value due to the rise in temperature, cutting off the electricity and welding the upper and lower sides quickly onto the frame, thus finishing the process of skin covering and resulting in residual stresses within the steel skin sheet.Type: GrantFiled: June 24, 1988Date of Patent: March 13, 1990Assignee: Jilin University of TechnologyInventors: Xicheng Jiang, Changgong Zhang, Yizhi Gao, Shiqiao Deng