Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Abstract: A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area.

Abstract: A semiconductor device that includes a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer includes a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of at least two suspended channel structures. The inner spacer may be composed of an n-type or p-type doped glass.

Abstract: A method of forming a semiconductor structure includes forming a recess within a semiconductor substrate, the recess is located between adjacent fins of a plurality of fins on the semiconductor substrate, forming a first liner above a perimeter including the recess, top surfaces of the semiconductor substrate, and top surfaces and sidewalls of the plurality of fins, the first liner includes a first oxide material, forming a second liner directly above the first liner, and forming a third liner directly above the second liner, the third liner includes a nitride material, the second liner includes a second oxide material capable of creating a dipole effect that neutralizes positive charges generated within the third liner and between the third liner and the first liner.

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.

Abstract: A technique relates to a semiconductor device. A stack is formed of alternating layers of inserted layers and channel layers on a substrate. Source or drain (S/D) regions are formed on opposite sides of the stack. The inserted layers are converted into oxide layers. Gate materials are formed on the stack.

Abstract: Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided.

Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate over a fin, which has a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer, to establish a channel region and source/drain regions. Source/drain extensions are grown on the lower semiconductor layer. Source/drain extensions are grown on the upper semiconductor layer. The dummy gate is replaced with a gate stack.

Abstract: A method for forming a semiconductor device comprises forming a fin on a substrate and forming a sacrificial gate over a channel region of the fin. A hydrogen terminated surface is formed on sidewalls of the sacrificial gate, and a spacer is deposited on the hydrogen terminated surface of the sacrificial gate. An insulator layer is formed over portions of the fin. The sacrificial gate is removed to expose the channel region of the fin, and a gate stack is formed over the channel region of the fin.

Abstract: Devices and methods for a vertical field effect transistor (VTFET) semiconductor device include recessing a gate dielectric and a gate conductor of a vertical gate structure below a top of a vertical fin to form openings between the top of the vertical fin and an etch stop layer, the top of the vertical fin being opposite to a substrate at a bottom of the vertical fin. A spacer material is deposited in the openings to form a spacer corresponding to each of the openings. Each spacer is recessed below the top of the vertical fin. A top spacer is selectively deposited in each of the openings to line the etch stop layer and the spacer such that the top of the vertical fin is exposed above the top spacer and the spacer is covered by the top spacer. A source/drain region is formed on the top of the vertical fin.

Abstract: Fabrication of a semiconductor structure includes forming a set of two or more fins on a source/drain region formed on a substrate. A first mask layer and a second mask layer are formed on each fin. A spacer layer is formed on the source/drain region and between each fin, and a dielectric layer is formed on the spacer layer and along an exterior of each fin. A plurality of gate metal portions is created each having a thickness about equal to a target thickness. The first mask layer and an exposed portion of the dielectric layer are removed from each fin. An interlayer dielectric is deposited on the semiconductor structure. Portions of the interlayer dielectric and the gate metal are removed to a top of the second mask layer. The gate metal portions are each recessed to substantially the same depth.

Abstract: Disclosed are methods and compositions for detection and amplification of nucleic acids, wherein two DNA strands hybridized to an RNA strand are ligated. In one aspect, the disclosed methods include removal of an energy source, such as ATP, upon charging a ligase to form an enzyme-AMP intermediate, and then adding substrate, which results in one complete round of RNA-templated DNA ligation. In another aspect, the ligation reaction is accomplished by use of a mixture of at least two different ligase enzymes. The disclosed methods and compositions for RNA-templated DNA ligation may be particularly useful for detection of RNA sequence variants, for example RNA splice variants, and for quantitative expression analysis.

Abstract: Techniques for forming VFETs with differing gate lengths Lg on the same wafer using a gas cluster ion beam (GCIB) process to produce fins of differing heights are provided. In one aspect, a method of forming fins having different heights includes: patterning the fins having a uniform height in a substrate, the fins including at least one first fin and at least one second fin; forming an oxide at a base of the at least one second fin using a low-temperature directional oxidation process (e.g., GCIB oxidation); and removing the oxide from the base of the at least one second fin to reveal the at least one first fin having a height H1 and the at least one second fin having a height H2, wherein H2>H1. VFETs and methods for forming VFETs having different fin heights using this process are also provided.

Abstract: A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on the substrate and around the at least one fin. A spacer layer is disposed on the bottom source/drain and around the at least one fin. A gate structure is disposed on the spacer layer and around the at least one fin. The gate length is the same or substantially the same on each side of the at least one fin.

Abstract: A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.

Abstract: A semiconductor wafer includes a substrate. The substrate includes a first substrate region doped with a first dopant and a second substrate region doped with a second dopant. The semiconductor wafer further includes a buried oxide (BOX) layer formed on the substrate and a channel layer formed above the BOX layer. A first transistor is operably disposed on the substrate in the first substrate region and a second transistor is operably disposed on the substrate in the second substrate region. First doped source and drain structures electrically connected to the substrate in the first substrate region and separated by portions of the channel layer and the BOX layer. Second doped source and drain structures electrically connected to the substrate in the second substrate region and separated by portions of the channel layer and the BOX layer.

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.

Abstract: Semiconductor device structures and techniques are provided for measuring contact resistance. A semiconductor device is disclosed including a first source/drain region and a contact disposed on the first source/drain region and configured to supply energy to the semiconductor device. A fin extends between the first source/drain region and a second source/drain region of the semiconductor device. A first contact material layer is disposed on the second source/drain region and a first active drain contact is disposed on the first contact material layer. A first sensor drain contact is also disposed on the first contact material layer. A second contact material layer is disposed on the second source/drain region and a second active drain contact is disposed on the second contact material layer. A third contact material layer is disposed on the second source/drain region and a second sensor drain contact is disposed on the third contact material layer.

Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.

Abstract: A sacrificial inner dielectric spacer is formed on physically exposed sidewalls of each recessed semiconductor channel material nanosheet of a nanosheet material stack that further includes recessed sacrificial semiconductor material nanosheets that have an inner dielectric spacer formed on physically exposed sidewalls thereof. A local isolation region is then formed by selective epitaxial growth on a surface of a semiconductor substrate containing the nanosheet material stack. After forming the local isolation region, the sacrificial inner dielectric spacers are removed and a source/drain region is formed on the physically exposed surface of each recessed semiconductor channel material nanosheet. A portion of the source/drain structure is formed in a gap located between each neighboring pair of vertically spaced apart inner dielectric spacers.