Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

Abstract: A method and structure for forming hybrid high mobility channel transistors. The method includes: providing a substrate, epitaxially growing a buffer layer over the substrate and a semiconductor layer over the buffer layer, forming a partial opening over the semiconductor layer, epitaxially growing a second semiconductor layer in the opening, forming a first plurality of fins from the first semiconductor layer and a second plurality of fins from the second semiconductor layer, where the first semiconductor layer and the second semiconductor material comprise different materials, oxidizing a portion of the second plurality of fins, and stripping the oxidized portion of the second plurality of fins, where after striping the oxidized portion of the second plurality of fins, the second plurality of fins have the same width as the first plurality of fins.

Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer.

Abstract: A method for manufacturing a semiconductor device includes forming a channel layer on a semiconductor substrate and forming at least two spacers on the channel layer. A first portion of a gate metal layer is formed between the spacers, and a dielectric layer is conformally deposited on the spacers and the first portion of the gate metal layer. In the method, part of the dielectric layer is directionally removed from surfaces which are parallel to an upper surface of the substrate. A second portion of the gate metal layer is formed between remaining portions of the dielectric layer and on the first portion of the gate metal layer, and a cap layer is deposited on the second portion of the gate metal layer. A lateral width the second portion of the gate metal layer is less than a lateral width of the first portion of the gate metal layer.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

Abstract: Embodiments of the invention are directed to a method of forming a nanosheet transistor. A non-limiting example of the method includes forming a nanosheet stack having alternating layers of channel nanosheets and sacrificial nanosheets, wherein each of the layers of channel nanosheets includes a first type of semiconductor material, and wherein each of the layers of sacrificial nanosheets includes a second type of semiconductor material. The layers of sacrificial nanosheets are removed from the nanosheet stack, and layers of replacement sacrificial nanosheets are formed in the spaces that were occupied by the sacrificial nanosheets. Each of the layers of replacement sacrificial nanosheets includes a first type of non-semiconductor material.

Abstract: A method for fabricating a stacked nanopore includes forming a stack of layers having alternating conductive lines and dielectric layers on a substrate, and patterning the stack to form a staircase structure with the conductive lines having a length gradually changing at each level in the stack. The method also includes depositing and planarizing a dielectric material over the staircase structure, forming contacts through the dielectric material to the conductive lines for each level of conductive lines, etching a nanopore through the stack of layers to form pairs of opposing electrodes across the nanopore using the conductive lines; and opening up the substrate to expose the nanopore.

Abstract: Structures and methods for making nanosheet structures with an electrically isolating feature associated therewith. The structure includes: a substrate, an epitaxial oxide layer over the substrate, a plurality of stacked nanosheets of semiconductor channel material over the epitaxial layer, and a source/drain semiconductor material located laterally adjacent and on each side of the plurality of stacked nanosheets of semiconductor channel material, where the plurality of nanosheets are decoupled from the source/drain semiconductor material by the epitaxial oxide layer.

Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

Abstract: A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.

Abstract: Embodiments of the invention form a channel fin across from a major surface of a substrate, wherein a top surface of the channel fin extends substantially horizontally with respect to the major surface. A gate is formed across from the major surface and along a sidewall surface of the channel fin, wherein a first top surface of the gate is above the top surface of the channel fin and extends substantially horizontally with respect to the major surface. A second top surface of the gate is defined by a trench formed through an exposed sidewall portion of the gate in a direction that is substantially horizontal with respect to the major surface, wherein a gate length dimension of the initial gate is defined by a distance from a bottom surface of the gate to the second top surface of the gate.

Abstract: A sensing device includes a stack of dielectric layers having conductive materials disposed between the dielectric layers. A nanopore is disposed through the stacks of dielectric layers and separates the conductive materials to provide electrodes on opposite sides of the nanopore. Contacts connect to each of the electrodes.

Abstract: Techniques for controlling top spacer thickness in VFETs are provided. In one aspect, a method of forming a VFET device includes: depositing a dielectric hardmask layer and a fin hardmask(s) on a wafer; patterning the dielectric hardmask layer and the wafer to form a fin(s) and a dielectric cap on the fin(s); forming a bottom source/drain at a base of the fin(s); forming bottom spacers on the bottom source/drain; forming a gate stack alongside the fin(s); burying the fin(s) in a dielectric fill material; selectively removing the fin hardmask(s); recessing the gate stack to form a cavity in the dielectric fill material; depositing a spacer material into the cavity; recessing the spacer material to form top spacers; removing the dielectric cap; and forming a top source/drain at a top of the fin(s). A VFET device is also provided.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.