Abstract: The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.

Abstract: A method for forming a semiconductor device includes forming first and second hard mask layers overlying a semiconductor substrate and forming trenches through the second hard mask, the first hard mask, and into the substrate. A dielectric material is formed in the trenches to form shallow trench isolation regions, removing the second hard mask layer, and a floating gate material is formed overlying the first hard mask and the trenches. The method further includes repeating at least twice a process of forming a buffer layer over the floating gate material and using a polishing process to remove a portion of the buffer layer and a top portion of the floating gate material. Next, a dry etch process to remove a portion of the floating gate material above the shallow trench isolation regions and the remaining portions of the buffer layer to form floating gate structures.

Abstract: A method is provided for fabricating a flash memory device. The method includes providing a semiconductor substrate; and forming a first polysilicon layer. The method also includes forming a hard mask layer; and forming a plurality of first openings exposing the first polysilicon layer in the hard mask layer and the first polysilicon layer. Further, the method includes forming a plurality of grooves by etching the semiconductor substrate along the first openings; and forming liner oxide layers by oxidizing the first polysilicon layer. Further, the method also includes forming shallow trench isolation structures by filling the first openings; and forming second openings by removing the hard mask layer and the non oxidized first polysilicon layer. Further, the method also includes forming a tunnel oxide layer on a bottom of the second opening; and forming a floating gate on each of the tunnel oxide layers.

Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.

Abstract: Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region.

Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a substrate can be provided. The substrate can have a plurality of isolation structures. A top surface of the plurality of isolation structures can be higher than a surface of the substrate. A device layer can be formed on the substrate and on the plurality of isolation structures. The device layer can be polished using a polishing process, such that the top surface of the plurality of isolation structures are exposed, with residue remaining on the device layer and on the plurality of isolation structures. The residue can be removed from the device layer and from the plurality of isolation structures using a non-polishing-removal process, such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially leveled and smooth.

Abstract: A semiconductor apparatus and a manufacturing method therefor is described. The semiconductor apparatus comprises a substrate and a gate structure for a N-channel semiconductor device above the substrate. A recess is formed at a lower end portion of at least one of two sides of the gate where it is adjacent to a source region and a drain region, of the N-channel semiconductor. The channel region of the N-channel semiconductor device has enhanced strain. The apparatus can further have a gate structure for a P-channel semiconductor device above the substrate.

Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region. A gate dielectric material layer is formed to cover the first region, and a control gate dielectric layer is formed over a surface portion of the second region. The control gate dielectric layer has a top surface higher than the gate dielectric layer. A gate material layer is conformally formed to cover an entire surface of the semiconductor substrate and has a top surface in the second region higher than a top surface in the first region. A first filling material layer is formed on the gate material layer. A first patterned mask layer is formed on the first filling material layer to form a gate on a gate dielectric layer in the first region. A control gate is formed on the control gate dielectric layer of the second region.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube portion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.

Abstract: According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.

Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.

Abstract: Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region.

Abstract: Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on the substrate and a dummy gate layer on the dummy gate dielectric layer. A dielectric layer is formed on the substrate and on sidewall surfaces of the dummy gate structure. A top surface of the dielectric layer is leveled with a top surface of the dummy gate structure. A barrier layer is formed on the dielectric layer for protecting the dielectric layer. The dummy gate layer and the dummy gate dielectric layer are removed, to form an opening in the dielectric layer without reducing a thickness of the dielectric layer. A gate dielectric layer is formed on sidewall surfaces and a bottom surface of the opening. A gate layer is formed on the gate dielectric layer to fill the opening.

Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a substrate can be provided. The substrate can have a plurality of isolation structures. A top surface of the plurality of isolation structures can be higher than a surface of the substrate. A device layer can be formed on the substrate and on the plurality of isolation structures. The device layer can be polished using a polishing process, such that the top surface of the plurality of isolation structures are exposed, with residue remaining on the device layer and on the plurality of isolation structures. The residue can be removed from the device layer and from the plurality of isolation structures using a non-polishing-removal process, such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially leveled and smooth.

Abstract: An electrically conductive device and a manufacturing method thereof are provided. According to an exemplary embodiment, an electrically conductive device includes a graphene layer on a substrate, a protein tube portion on the graphene layer, and a conductor penetrating through the protein tube potion to the graphene layer, wherein the conductor is in electrical contact with the graphene layer.

Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.

Abstract: Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region. A gate dielectric material layer is formed to cover the first region, and a control gate dielectric layer is formed over a surface portion of the second region. The control gate dielectric layer has a top surface higher than the gate dielectric layer. A gate material layer is conformally formed to cover an entire surface of the semiconductor substrate and has a top surface in the second region higher than a top surface in the first region. A first filling material layer is formed on the gate material layer. A first patterned mask layer is formed on the first filling material layer to form a gate on a gate dielectric layer in the first region. A control gate is formed on the control gate dielectric layer of the second region.

Abstract: Semiconductor devices and fabrication methods are provided. A fin can be formed on a semiconductor substrate, a gate can be formed across the fin, and sidewall spacers can be formed across the fin on both sides of the gate. A dummy contact can be formed across the fin and on each of the both sides of the sidewall spacers. After forming an interlayer dielectric layer on the semiconductor substrate, the dummy contact can be removed to form a contact trench. The dummy contact is made of a material having an etch selectivity sufficiently higher than the fin such that the removing of the dummy contact generates substantially no damage to the fin. A conductive material can be filled in the contact trench to form a trench metal contact.