Patents by Inventor Xiong Zhang

Xiong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10373244
    Abstract: A system and method for virtual clothes fitting based on video augmented reality in a mobile wireless device is disclosed. In an embodiment, a method for virtual cloth-fitting with video augmentation in a mobile wireless device includes receiving a video stream of an upper body of a user; detecting a face in the video stream; detecting a shoulder contour; determining keypoints of the shoulder and neck portions of the video stream of the upper body of the user according to the detected face and the detected shoulder contour; mapping an image of clothes to the video stream of the upper body of the user according to the keypoints; and displaying an augmented video stream of the upper body of the user with the image of the clothes overlaid over a portion of the video stream of the upper body of the user.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: August 6, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Jingsong Xu, Ying Cui, Qiang Wu, Jian Zhang, Chen-Xiong Zhang, Haibo Liu, Kui Fang
  • Publication number: 20190212039
    Abstract: A double-sided roll bond condenser has a main body, an interposition section, and a neck portion. The main body is an upright board and has two side surfaces. Two filling structures are respectively protruded from the two side surfaces of the main body. The interposition section is formed at a bottom portion of the double-side roll bond condenser, and is a U-shaped folded structure. The U-shaped folded structure protrudes from one of the two side surfaces of the main body. The neck portion is located between the main body and the interposition section.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 11, 2019
    Inventors: Xiong Zhang, Jie Zhou
  • Publication number: 20190210880
    Abstract: Provided are a graphene and a preparation method therefor. The method for preparing a graphene comprises following steps: i) placing a mixture of a magnesium powder and a solid oxide powder in a carbon dioxide-containing environment; and ii) heating the mixture to enable the magnesium powder to react with carbon dioxide, thereby obtaining a graphene. The specific surface area of the grapheme is 350-750 m2/g, and the pore volume is 1-2 cm3/g. The method for preparing a graphene in the present invention is simple and easy to carry out, and has a low cost and a high yield; and the graphene product has few impurities, a high carbon-oxygen ratio, and excellent capacitance performance and electrochemical stability.
    Type: Application
    Filed: March 10, 2017
    Publication date: July 11, 2019
    Inventors: Yanwei MA, Chen LI, Xiong ZHANG
  • Patent number: 10333748
    Abstract: The present invention discloses an adaptive parameter adjustment method for a hybrid precoding millimeter-wave transmission system. The method includes the following step: interacting between a transmitter and a receiver for a number of radio frequency chains that need to be established. The receiver calculates, according to a received signal power at the time of established a different number of radio frequency chains and a total power consumption at the time of established the different number of radio frequency chains, the number of the radio frequency chains that need to be established. According to the present invention, under a condition of balancing power consumption and a rate, a number of radio frequency chains that need to be established is adaptively selected, so as to optimally configure power consumption and a transmission rate in a millimeter-wave transmission system.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: June 25, 2019
    Assignee: SHANGHAI RESEARCH CENTER FOR WIRELESS COMMUNICATIONS
    Inventors: Xiu-mei Yang, Wu-xiong Zhang, Meng-ying Zhang, Yang Yang, Hai-feng Wang
  • Patent number: 10326995
    Abstract: System and method embodiments are provided for achieving improved View Synthesis Distortion (VSD) calculation and more accurate distortion estimation of encoded video frames. An embodiment method includes obtaining a depth map value for a video frame and determining a weighting factor for depth distortion in accordance with the depth map value. The weighting factor maps a pixel range of the depth map value to an output function having higher values for closer image objects and lower values for farther image objects. The VSD for the video frame is then calculated as a function of absolute horizontal texture gradients weighted by a depth distortion value and the weighting factor determined in accordance with the depth map value.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 18, 2019
    Assignees: Futurewei Technologies, Inc., Santa Clara University
    Inventors: Zhouye Gu, Nam Ling, Chen-Xiong Zhang, Jianhua Zheng
  • Patent number: 10309436
    Abstract: Provided is a single-groove and short-tail pulling rivet and an erection method thereof, and the pulling rivet comprises a single groove and a short tail having a broached groove with a continuous and smooth cambered surface, and is characterized by easy manufacturing, low cost and convenient erection. The broached groove is an arc surface with three sections of different radiuses, which solves stress concentration and sticking of a single-groove and short-tail rivet during riveting, and allows a claw of a riveting machine to be engaged to the best position automatically. The tooth profile of a locking groove section of the rivet is a curve combining an arc and a straight line, which greatly improves fastening force.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 4, 2019
    Assignee: MEISHAN CRRC FASTENING SYSTEM CO., LTD.
    Inventors: Xu He, Yu Liu, Kai Fu, Xiong Zhang, Yunlong Jia, Guangcheng Dai, Xinrong Li, Xia Wang, Yong Wan
  • Patent number: 10306266
    Abstract: A method, an apparatus and a decoder for decoding a block of a depth map are provided. An ordered list of decoding modes is obtained, wherein the ordered list of decoding modes comprises a plurality of decoding modes each of which is capable of being used for decoding of the block. A plurality of depth modeling modes (DMMs) each of which is capable of being used for decoding of the block are obtained. And whether a DMM of the plurality of DMMs is to be added into the ordered list of decoding modes in accordance with a decision condition is determined.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 28, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Zhouye Gu, Jianhua Zheng, Nam Ling, Chen-Xiong Zhang
  • Publication number: 20190156235
    Abstract: A phase shifter, a quantum logic gate apparatus, an optical quantum computing apparatus, and a phase shift method, where the phase shifter includes an optical resonant cavity and a quantum point, where a resonance frequency of the optical resonant cavity is ?c, the quantum point is located in the optical resonant cavity, and a transition frequency of the quantum point is ?x, the quantum point and the optical resonant cavity are coupled to form a coupled system, and a transition energy difference of the coupled system is determined by ?c, ?x, and a coupling strength between the quantum point and the optical resonant cavity (g), and ?x is set.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Wen Zhang, Chen-Xiong Zhang
  • Publication number: 20190148534
    Abstract: The application discloses a tunneling field-effect transistor, including: a substrate layer; a rectangular semiconductor strip formed on an upper surface of the substrate layer, where the rectangular semiconductor strip includes a first source region, a first channel region, a drain region, a second channel region, and a second source region that are disposed in sequence along a first direction; a first gate dielectric layer covering an outer surface of a first part of the first source region and a second gate dielectric layer covering an outer surface of a third part of the second source region.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 16, 2019
    Inventors: Jing ZHAO, Chen-Xiong ZHANG
  • Patent number: 10270391
    Abstract: A differential input amplification-stage circuit comprises a voltage unit, first and second bulk-driven transistors, first and second mirror current sources, and a differential amplifier unit. The first and the second bulk-driven transistors respectively receive first and second input voltages, and converts the first and the second input voltages into first and second output currents. The differential amplifier unit separately outputs first and second adjustment currents under an action of voltages output by the first to the third voltage output ends. The first and the second mirror current sources respectively output first and second predetermined currents according to the first output current and the first adjustment current, and the second output current and the second adjustment current, so as to maintain transconductance constancy of the differential input amplification-stage circuit. Therefore, output stability is improved.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yangyang Tang, Chen-Xiong Zhang
  • Patent number: 10249744
    Abstract: A tunnel field-effect transistor and a method for manufacturing a tunnel field-effect transistor is disclosed. Source regions are located on two sides of an oxide structure, an epitaxial layer is located on a surface on a side that is of the source region and that is away from the oxide structure, and a gate structure is located on a surface on a side that is of the epitaxial layer and that is away from the source region, so that a gate electric field direction of the tunnel field-effect transistor is the same as an electron tunneling direction, and carriers on a valence band of the source region tunnel to a conduction band of the epitaxial layer at relatively high tunneling efficiency, thereby generating a steep subthreshold swing and enabling a subthreshold swing value of the tunnel field-effect transistor to be lower than 60 mV/dec to consume relatively low power.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 2, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jing Zhao, Chen-Xiong Zhang
  • Publication number: 20190094397
    Abstract: A system and method for hydraulic fracturing and monitoring microseismic events related to hydraulic fracturing are described. One method describes a method of hydraulic fracturing gas production comprising drilling and casing a gas production well with a horizontal section within a formation layer, perforating the horizontal section of the well at a known location, and monitoring the resulting seismic waves using an array of geophones. Using the seismic waves resulting from the perforation shot, subsequent microseismic events may be located using a root mean square velocity and average velocity and without the use of a depth velocity model.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 28, 2019
    Applicant: REAL TIME GEOMECHANICS, LLC
    Inventors: Jie Zhang, Wei Zhang, Xiong Zhang
  • Publication number: 20190077686
    Abstract: A zero discharge process for separating sludge and salt from desulfurization wastewater includes a pretreatment process, a membrane treatment process and an evaporative crystallization process; in the pretreatment process, the desulfurization wastewater enters a raw water tank, an aeration fan introduces compressed air into the raw water tank, and the wastewater is lifted to first-stage reaction and clarification by a raw water pump; in the membrane treatment process, the incoming wastewater is first filtered by ultrafiltration, then enters a pH adjustment tank, and is pumped into a nanofiltration membrane separation system and a reverse osmosis membrane separation system; in the evaporative crystallization process, the incoming wastewater is first subjected to two-stage preheating, then enters a degasser, and finally enters an evaporative concentration system and a crystallization system.
    Type: Application
    Filed: April 18, 2017
    Publication date: March 14, 2019
    Inventors: Xianhua JI, Wulin LI, Kuan LI, Zhenguo ZENG, Hui XU, Chen WANG, Qinqin LIU, Xiong ZHANG, Feng YAN, Xin LU
  • Publication number: 20190019897
    Abstract: A field effect transistor and a manufacturing method thereof are provided. The field effect transistor includes two top gate structures (1031C and 1031D) and two bottom gate structures (1032A and 1032B). The top gate structures (1031C and 1031D) and the bottom gate structures (1032A and 1032B) are opposite to each other in pair. This increases a quantity of control-voltage-induced carriers in the field effect transistor, and therefore increases an output current of the field effect transistor, improves a power gain limit frequency in high-frequency use, and makes an electric field between the top gate structures (1031C and 1031D) and the bottom gate structures (1032A and 1032B) more adequately cover a channel layer (106) between source structures (1041 and 1042) and a drain (105), thereby reducing a parasitic effect in a high frequency, and further improving a frequency characteristic of the field effect transistor.
    Type: Application
    Filed: August 31, 2018
    Publication date: January 17, 2019
    Inventors: Xudong QIN, Huilong XU, Chen-Xiong ZHANG
  • Publication number: 20190013413
    Abstract: The present disclosure relates to a tunneling field-effect transistor and a fabrication method. One example transistor includes a semiconductor substrate, a semiconductor nanosheet, a source region and a drain region, a dielectric layer, and a gate metal layer. The semiconductor nanosheet is vertically disposed on the semiconductor substrate. The source region and the drain region are connected using a channel. The drain region, the channel, and the source region are disposed on the semiconductor nanosheet in turn. The drain region is in contact with the semiconductor substrate. The source region is located at an end, of the semiconductor nanosheet, far away from the semiconductor substrate. The dielectric layer comprises at least a gate dielectric layer, is disposed on a surface of the semiconductor nanosheet, and surrounds the channel. The gate metal layer is disposed on a surface of the gate dielectric layer and surrounds the gate dielectric layer.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 10, 2019
    Inventors: Xichao YANG, Chen-Xiong ZHANG
  • Patent number: 10173399
    Abstract: The present disclosure discloses an anti-yellowing composition comprising at least a phosphorus-containing compound and at least a pentaerythritol ester, wherein the phosphorus-containing compound is selected from a phosphate salt, and a concentration of the phosphorus-containing compound is 100-1600 parts by weight, relative to 100 parts by weight of the pentaerythritol ester. The present disclosure also discloses a resin composition containing the anti-yellowing composition, and a metal-resin composite formed with the resin composition and a metal substrate, and a preparation method and use thereof. The present disclosure further discloses an electronic product shell formed with the resin composition and a metal shell body.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 8, 2019
    Assignee: BYD Company Limited
    Inventors: Xiong Zhang, Shouping Bai, Qianrong Zhang, Wei Zhou, Qing Gong
  • Patent number: 10141434
    Abstract: A complementary tunneling field effect transistor and a manufacturing method are disclosed, which includes: a first drain region and a first source region that are disposed on a substrate, where they include a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, where they include a second dopant; a first epitaxial layer that is disposed on the first drain region and the second source region, and a second epitaxial layer that is disposed on the second drain region and the first source region; and a first gate stack layer that is disposed on the first epitaxial layer, and a second gate stack layer that is disposed on the second epitaxial layer.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: November 27, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xichao Yang, Jing Zhao, Chen-Xiong Zhang
  • Publication number: 20180323291
    Abstract: A semiconductor device and a method for fabricating a semiconductor device are disclosed. The semiconductor device includes a tunnel field-effect transistor and a planar device. The tunnel field-effect transistor includes a first substrate and a first electrical element, and the first electrical element is formed on one side of the first substrate; the planar device includes a second substrate and a second electrical element, the second substrate and the first substrate are an integrated structure and form a main substrate, the second electrical element is formed on one side of the second substrate, and the second electrical element and the first electrical element are disposed on a same side of the main substrate; and the planar device includes any one of a metal oxide semiconductor transistor, a capacitor, and a resistor.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Inventors: Jing Zhao, Chen-Xiong Zhang
  • Publication number: 20180295386
    Abstract: An apparatus including a memory operably coupled to a processor. The processor is configured to select an intra smoothing filter for a rectangular prediction unit (PU) based on a lookup table (LUT) used for square PUs, wherein a width of the rectangular PU is different from a height of the rectangular PU.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 11, 2018
    Inventors: Guichun Li, Lingzhi Liu, Changcai Lai, Nam Ling, Jianhua Zheng, Chen-Xiong Zhang
  • Patent number: 10097838
    Abstract: A method for coding a coding unit that is coded with a single sample value is provided. The method selects a coding pattern from at least two predetermined coding patterns, each of which includes a plurality of boundary neighboring samples of the coding unit that have been reconstructed, and decodes the coding unit according to a value of at least one of the plurality of boundary neighboring samples of the selected coding pattern that is available.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: October 9, 2018
    Assignees: Futurewei Technologies, Inc., Santa Clara University
    Inventors: Jianhua Zheng, Zhouye Gu, Chen-Xiong Zhang, Nam Ling