Patents by Inventor Xiuyu Cai

Xiuyu Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446665
    Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Ying Hao Hsieh
  • Patent number: 10388754
    Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: August 20, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 10361311
    Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 23, 2019
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie
  • Patent number: 10355020
    Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: July 16, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10355086
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 16, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20190206868
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Application
    Filed: March 6, 2019
    Publication date: July 4, 2019
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • Publication number: 20190198553
    Abstract: An example image sensor structure includes an image layer. The image layer includes an array of light detectors disposed therein. A device stack is disposed over the image layer. An array of light guides is disposed in the device stack. Each light guide is associated with at least one light detector of the array of light detectors. A passivation stack is disposed over the device stack. The passivation stack includes a bottom surface in direct contact with a top surface of the light guides. An array of nanowells is disposed in a top layer of the passivation stack. Each nanowell is associated with a light guide of the array of light guides. A crosstalk blocking metal structure is disposed in the passivation stack. The crosstalk blocking metal structure reduces crosstalk within the passivation stack.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 27, 2019
    Applicant: Illumina, Inc.
    Inventors: Xiuyu CAI, Ali AGAH, Tracy H. FUNG, Dietrich DEHLINGER
  • Publication number: 20190196108
    Abstract: Light detection devices and corresponding methods are provided. The devices include a reaction structure to contain a reaction solution and at least one reaction site that generates light emissions in response to incident excitation light after treatment with the reaction solution. The devices also include a plurality of light sensors and device circuitry. The devices further include a plurality of light guides extending toward at least one corresponding light sensor from input regions that receive the excitation light and the light emissions from at least one corresponding reaction recess. The light guides comprise a first filter region that filters the excitation light and permits the light emissions of a first wavelength to pass to the at least one corresponding light sensor, and a second filter region that filters the excitation light and the permits light emissions of a second wavelength to pass to the at least one corresponding light sensor.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 27, 2019
    Applicant: Illumina, Inc.
    Inventor: Xiuyu CAI
  • Publication number: 20190195797
    Abstract: Light detection devices and related methods are provided. The devices may comprise a reaction structure for containing a reaction solution with a relatively high or low pH and a plurality of reaction sites that generate light emissions. The devices may comprise a device base comprising a plurality of light sensors, device circuitry coupled to the light sensors, and a plurality of light guides that block excitation light but permit the light emissions to pass to a light sensor. The device base may also include a shield layer extending about each light guide between each light guide and the device circuitry, and a protection layer that is chemically inert with respect to the reaction solution extending about each light guide between each light guide and the shield layer. The protection layer prevents reaction solution that passes through the reaction structure and the light guide from interacting with the device circuitry.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 27, 2019
    Applicant: Illumina, Inc.
    Inventors: Xiuyu CAI, Joseph Francis PINTO, Thomas A. BAKER, Tracy Helen FUNG
  • Publication number: 20190148557
    Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 16, 2019
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie
  • Patent number: 10290636
    Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 14, 2019
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Qing Liu, Chun-chen Yeh, Ruilong Xie, Xiuyu Cai
  • Patent number: 10276573
    Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 30, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10256304
    Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate including an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: April 9, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., GLOBALFOUNDRIES, INC.
    Inventors: Xiuyu Cai, Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 10249726
    Abstract: One illustrative example of a transistor device disclosed herein includes, among other things, a gate structure, first and second spacers positioned adjacent opposite sides of the gate structure, and a multi-layer gate cap structure positioned above the gate structure and the upper surface of the spacers. The multi-layer gate cap structure includes a first gate cap material layer positioned on an upper surface of the gate structure and on the upper surfaces of the first and second spacers, a first high-k protection layer positioned on an upper surface of the first gate cap material layer and a second gate cap material layer positioned on an upper surface of the high-k protection layer. The first and second gate cap layers comprise different materials than the first high-k protection layer.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Xiuyu Cai
  • Patent number: 10217869
    Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie
  • Patent number: 10153371
    Abstract: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 11, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie
  • Patent number: 10134840
    Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: November 20, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Chun-Chen Yeh, Xiuyu Cai, Qing Liu, Ruilong Xie
  • Patent number: 10134903
    Abstract: A method forms a vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are formed adjacent respective sidewalls of the semiconductor substrate. The method forms dielectric material separating the gate electrodes from the source and drain regions.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 20, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Xiuyu Cai, Chun-chen Yeh, Ruilong Xie
  • Publication number: 20180277648
    Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.
    Type: Application
    Filed: May 22, 2018
    Publication date: September 27, 2018
    Inventors: Xiuyu Cai, Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita
  • Patent number: 10062762
    Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: August 28, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Xiuyu Cai, Chun-chen Yeh, Ruilong Xie