Abstract: Methods for forming a semiconductor device include forming a first spacer on a plurality of fins. A second spacer is formed on the first spacer, the second spacer being formed from a different material from the first spacer. Gaps between the fins are filled with a support material. The first spacer and second spacer are polished to expose a top surface of the plurality of fins. All of the support material is etched away after polishing the first spacer and second spacer. The plurality of fins is etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

Abstract: Flow cells systems and corresponding methods are provided. The flow cells systems may include a socket comprising a base portion, a plurality of electrical contacts and a cover portion that includes a first port. The flow cells systems may also include a flow cell device secured within an enclosure of the socket. The flow cell device may comprise a frameless light detection device comprising a base wafer portion, a plurality of dielectric layers, a reaction structure, a plurality of light guides, a plurality of light sensors, and device circuitry electrically coupled to the light sensors. The flow cell device may also comprise a lid forming a flow channel over the reaction structure that includes a second port in communication with the flow channel and the first port of the socket. The device circuity of the light detection device may be electrically coupled to the electrical contacts of the socket.

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

Abstract: Light detection devices and corresponding methods are provided. The devices include a reaction structure to contain a reaction solution and at least one reaction site that generates light emissions in response to incident excitation light after treatment with the reaction solution. The devices also include a plurality of light sensors and device circuitry. The devices further include a plurality of light guides extending toward at least one corresponding light sensor from input regions that receive the excitation light and the light emissions from at least one corresponding reaction recess. The light guides comprise a first filter region that filters the excitation light and permits the light emissions of a first wavelength to pass to the at least one corresponding light sensor, and a second filter region that filters the excitation light and the permits light emissions of a second wavelength to pass to the at least one corresponding light sensor.

Abstract: An example sensor includes a flow cell, a detection device, and a controller. The flow cell includes a passivation layer having opposed surfaces and a reaction site at a first of the opposed surfaces. The flow cell also includes a lid operatively connected to the passivation layer to partially define a flow channel between the lid and the reaction site. The detection device is in contact with a second of the opposed surfaces of the passivation layer, and includes an embedded metal layer that is electrically isolated from other detection circuitry of the detection device. The controller is to ground the embedded metal layer.

Abstract: Disclosed is an apparatus and method of forming, including a supporting structure, a sensor on the supporting structure, a pair of columns on the supporting structure at opposite sides of the sensor, the pair of columns having a column height relative to a top surface of the supporting structure, the column height being higher than a height of the active surface of the sensor relative to the top surface of the supporting structure, and a lidding layer on the pair of columns and over the active surface, the lidding layer being supported at opposite ends by the pair of columns. The active surface of the sensor, the lidding layer and the pair of columns form an opening above at least more than about half of the active surface of the sensor, and the supporting structure, the sensor, the lidding layer and the pair of columns together form a flow cell.

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

Abstract: Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is deposited adjacent a transistor gate. An outer spacer of a different material is deposited adjacent the inner spacer. Stressor cavities are formed adjacent the transistor gate. The inner spacer is recessed, forming a divot. The divot is filled with a material to protect the transistor gate. The stressor cavities are then filled. As the gate is safely protected, unwanted epitaxial growth (“mouse ears”) on the transistor gate is prevented.

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.

Abstract: A semiconductor structure includes a substrate, and a replacement metal gate (RMG) structure is attached to the substrate. The RMG structure includes a lower portion and an upper tapered portion. A source junction is disposed on the substrate and attached to a first low-k spacer portion. A drain junction is disposed on the substrate and attached to a second low-k spacer portion. A first oxide layer is disposed on the source junction, and attached to the first low-k spacer portion. A second oxide layer is disposed on the drain junction, and attached to the second low-k spacer portion. A cap layer is disposed on a top surface layer of the RMG structure and attached to the first oxide layer and the second oxide layer.

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: A semiconductor substrate includes a bulk substrate layer that extends along a first axis to define a width and a second axis perpendicular to the first axis to define a height. A plurality of hetero semiconductor fins includes an epitaxial material formed on a first region of the bulk substrate layer. A plurality of non-hetero semiconductor fins is formed on a second region of the bulk substrate layer different from the first region. The non-hetero semiconductor fins are integrally formed from the bulk substrate layer such that the material of the non-hetero semiconductor fins is different from the epitaxial material.

Abstract: Light detection devices and related methods are provided. The devices may comprise a reaction structure for containing a reaction solution with a relatively high or low pH and a plurality of reaction sites that generate light emissions. The devices may comprise a device base comprising a plurality of light sensors, device circuitry coupled to the light sensors, and a plurality of light guides that block excitation light but permit the light emissions to pass to a light sensor. The device base may also include a shield layer extending about each light guide between each light guide and the device circuitry, and a protection layer that is chemically inert with respect to the reaction solution extending about each light guide between each light guide and the shield layer. The protection layer prevents reaction solution that passes through the reaction structure and the light guide from interacting with the device circuitry.

Abstract: Light detection devices and corresponding methods are provided. The devices include a reaction structure to contain a reaction solution and at least one reaction site that generates light emissions in response to incident excitation light after treatment with the reaction solution. The devices also include a plurality of light sensors and device circuitry. The devices further include a plurality of light guides extending toward at least one corresponding light sensor from input regions that receive the excitation light and the light emissions from at least one corresponding reaction recess. The light guides comprise a first filter region that filters the excitation light and permits the light emissions of a first wavelength to pass to the at least one corresponding light sensor, and a second filter region that filters the excitation light and the permits light emissions of a second wavelength to pass to the at least one corresponding light sensor.

Abstract: An example image sensor structure includes an image layer. The image layer includes an array of light detectors disposed therein. A device stack is disposed over the image layer. An array of light guides is disposed in the device stack. Each light guide is associated with at least one light detector of the array of light detectors. A passivation stack is disposed over the device stack. The passivation stack includes a bottom surface in direct contact with a top surface of the light guides. An array of nanowells is disposed in a top layer of the passivation stack. Each nanowell is associated with a light guide of the array of light guides. A crosstalk blocking metal structure is disposed in the passivation stack. The crosstalk blocking metal structure reduces crosstalk within the passivation stack.