Abstract: One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Abstract: One method disclosed includes, among other things, conformably depositing a layer of contact insulating material and a conductive material layer in a contact opening, forming a reduced-thickness sacrificial material layer in the contact opening so as to expose a portion, but not all, of the conductive material layer, removing portions of the conductive material layer and the layer of contact insulating material positioned above the upper surface of the reduced-thickness sacrificial material layer, removing the reduced-thickness sacrificial material layer, and forming a conductive contact in the contact opening that contacts the recessed portions of the conductive material layer and the layer of contact insulating material.

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract: A method for forming a gate of a semiconductor device includes providing a semiconductor substrate, forming an active region with trench isolation in the semiconductor substrate, providing a polysilicon layer disposed on the semiconductor substrate, and providing a hard mask layer disposed on the polysilicon layer. An ash resistant layer is disposed on the hard mask layer. Patterned portions of the ash resistant layer, the hard mask, and the polysilicon layer are moved, and the remaining portions of the ash resistant layer is wherein the patterned polysilicon layer defines the gate. The resistant layer inhibits or reduces the likelihood of pitting of the polysilicon layer and substrate during subsequent etching processes.

Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

Abstract: Methods and structures for forming short-channel finFETs with vertical and abrupt source and drain junctions are described. During fabrication, source and drain regions of the finFET may be recessed vertically and laterally under gate spacers. A buffer having a high dopant density may be formed on vertical sidewalls of the channel region after recessing the fin. Raised source and drain structures may be formed at the recessed source and drain regions. The raised source and drain structures may impart strain to the channel region.

Abstract: Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, an integrated circuit includes a semiconductor substrate and a replacement metal gate structure overlying the semiconductor substrate. The replacement metal gate structure includes a first metal and a second metal and has a recess surface formed by the first metal and the second metal. The first metal and the second metal include a first species of diffused foreign ions. The integrated circuit further includes a metal fill material overlying the recess surface formed by the first metal and the second metal.

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.