Abstract: One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.

Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In an embodiment, a method for fabricating a semiconductor device includes forming on a semiconductor surface a temporary gate structure including a polysilicon gate and a cap. A spacer is formed around the temporary gate structure. The cap and a portion of the spacer are removed. A uniform liner is deposited overlying the polysilicon gate. The method removes a portion of the uniform liner overlying the polysilicon gate and the polysilicon gate to form a gate trench. Then, a replacement metal gate is formed in the gate trench.

Abstract: A fin field effect transistor integrated circuit (FinFET IC) has a plurality of fins extending from a semiconductor substrate, where a trough is defined between adjacent fins. A second dielectric is positioned within the trough, and a protruding portion of the fins extends above the second dielectric. A first dielectric is positioned between the fin sidewalls and the second dielectric.

Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

Abstract: Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material that exposes at least a portion of a conductive structure, forming a layer of sacrificial material that covers the exposed portion of the conductive structure, with the layer of sacrificial material in position, performing at least one second etching process to remove the patterned hard mask while leaving the layer of sacrificial material in position within the cavity, and removing the layer of sacrificial material positioned within the cavity.

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract: Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract: One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.