Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

Abstract: Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.

Abstract: An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract: A replacement gate structure that includes a conductive metal gate electrode is formed in a gate cavity, wherein the gate cavity is formed in a dielectric material formed above an active region of a semiconductor device. An upper surface of the conductive metal gate electrode and an upper surface of the dielectric material are planarized during a common planarization process, and a protective conductive cap is selectively formed on and in direct physical contact with the planarized upper surface of the conductive metal gate electrode. A contact structure is formed in a dielectric insulating layer formed above the replacement gate structure, the contact structure directly contacting the protective conductive cap.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin having an upper surface and a plurality of side surfaces, forming a sacrificial gate structure comprised of a low-density oxide material having a density of less than 1.8 g/cm3 on and in contact with the upper surface and the side surfaces of the fin and a sacrificial gate material positioned on and in contact with the upper surface of the low-density oxide material, and forming a sidewall spacer adjacent the sacrificial gate structure. The method further includes removing the sacrificial gate material so as to thereby expose the low-density oxide material, so as to define a replacement gate cavity, and forming a replacement gate structure in the replacement gate cavity.

Abstract: One illustrative method disclosed herein includes, among other things, forming an inverted, generally T-shaped mandrel feature having a base mandrel structure and a substantially vertically oriented fin mandrel structure, the base mandrel structure having a lateral width that is greater than a lateral width of the fin mandrel structure, forming a sidewall spacer adjacent the sidewalls of the base mandrel structure and the fin mandrel structure, performing at least one etching process to remove portions of the inverted, generally T-shaped mandrel feature not covered by a sidewall spacer, wherein, after the etching process is completed, the sidewall spacers and remaining portions of the mandrel feature, collectively, define a fin pattern, and performing at least one additional process operation to form a plurality of fins in the substrate that correspond to the fin pattern.

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract: A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

Abstract: Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.

Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

Abstract: A device includes first and second fins defined in a semiconductor substrate and a raised isolation post structure positioned between the first and second fins, wherein an upper surface of the raised isolation post structure is at a level that is approximately equal to or greater than a level corresponding to an upper surface of each of the first and second fins. A first space is defined by a sidewall of the first fin and a first sidewall of the raised isolation post structure, a second space is defined by a sidewall of the second fin and a second sidewall of the raised isolation post structure, and a gate structure is positioned around a portion of each of the first and second fins and around a portion of the raised isolation post structure, wherein at least portions of the gate structure are positioned in the first and second spaces.

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract: A method includes forming a plurality of fin elements above a substrate. A mask is formed above the substrate. The mask has an opening defined above at least one selected fin element of the plurality of fin elements. An ion species is implanted into the at least one selected fin element through the opening to increase its etch characteristics relative to the other fin elements. The at least one selected fin element is removed selectively relative to the other fin elements.

Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.