METHODS OF FORMING CONDUCTIVE STRUCTURES USING A SACRIFICIAL MATERIAL DURING A METAL HARD MASK REMOVAL PROCESS
One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the layer of insulating material, performing at least one etching process to define a cavity in the layer of insulating material, forming a layer of sacrificial material so as to overfill the cavity, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity.
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1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming conductive structures, such as conductive contacts and conductive lines/vias, using a sacrificial material during the process of removing a metal hard mask layer used in forming such conductive structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To improve the operating speed of field effect transistors (FETs), and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs and the overall functionality of the circuit. Further scaling (reduction in size) of the channel length of transistors is anticipated in the future. While this ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size of the conductive contact elements and structures, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same level on which the circuit elements, such as transistors, are manufactured. Rather, modern integrated circuit products have multiple so-called metallization layer levels that, collectively, contain the “wiring” pattern for the product, i.e., the conductive structures that provide electrical connection to the transistors and the circuits, such as conductive vias and conductive metal lines. In general, the conductive metal lines are used to provide intra-level (same level) electrical connections, while inter-level (between levels) connections or vertical connections are referred to as vias. In short, the vertically oriented conductive via structures provide the electrical connection between the various stacked metallization layers. Accordingly, the electrical resistance of such conductive structures, e.g., lines and vias, becomes a significant issue in the overall design of an integrated circuit product, since the cross-sectional area of these elements is correspondingly decreased, which may have a significant influence on the effective electrical resistance and overall performance of the final product or circuit.
Improving the functionality and performance capability of various metallization systems has also become an important aspect of designing modern semiconductor devices. One example of such improvements is reflected in the increased use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than about 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias. The use of low-k dielectric materials tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk, as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials, they tend to be mechanically weaker than other common insulating materials, such as silicon dioxide, that have a higher dielectric constant and they may be more susceptible to chemical attack from various solutions that they are exposed to during processing operations.
One such problem will be discussed with reference
After the openings 24 are formed as depicted in
After the openings 24 are formed as depicted in
The present disclosure is directed to various methods of forming conductive structures using a sacrificial material during the process of removing a metal hard mask layer used in forming such conductive structures that may solve or at least reduce some of the problems identified above.
SUMMARY OF THE INVENTIONThe following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods of forming conductive structures, such as conductive contacts and conductive lines/vias, using a sacrificial material during the process of removing a metal hard mask layer used in forming such conductive structures. One illustrative method disclosed herein includes forming at least one layer of insulating material above a conductive structure, forming a patterned hard mask comprised of metal above the at least one layer of insulating material, performing at least one etching process through the patterned hard mask to define a cavity in the at least one layer of insulating material, wherein the cavity exposes at least a portion of the conductive structure, forming a layer of sacrificial material so as to overfill the cavity and cover the exposed portion of the conductive structure, performing at least one planarization process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity so as to thereby expose the exposed portion of the conductive structure.
Another illustrative method disclosed herein includes forming at least one layer of insulating material having a k value less than 3.3 above a conductive structure, forming a patterned hard mask comprised of metal above the at least one layer of insulating material, performing at least one etching process through the patterned hard mask to define a cavity in the at least one layer of insulating material, wherein the cavity exposes at least a portion of the conductive structure, forming a layer of sacrificial material so as to overfill the cavity and cover the exposed portion of the conductive structure, performing at least one chemical mechanical polishing process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity so as to thereby expose the exposed portion of the conductive structure.
Yet another illustrative method disclosed herein includes forming at least one layer of insulating material having a k value less than 3.3 above a conductive structure, forming a patterned hard mask comprised of metal above the at least one layer of insulating material, performing at least one etching process through the patterned hard mask to define a cavity in the at least one layer of insulating material, wherein the cavity exposes at least a portion of the conductive structure, forming a layer of sacrificial material comprised of flowable oxide so as to overfill the cavity and cover the exposed portion of the conductive structure, performing at least one chemical mechanical polishing process to remove a portion of the layer of sacrificial material and the patterned hard mask while leaving a remaining portion of the layer of sacrificial material within the cavity, and removing the remaining portion of the layer of sacrificial material positioned within the cavity so as to thereby expose the exposed portion of the conductive structure.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
DETAILED DESCRIPTIONVarious illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure is directed to various methods of forming conductive structures, such as conductive contacts and conductive lines/vias, using a sacrificial material during the process of removing a metal hard mask layer used in forming such conductive structures. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the methods disclosed herein may be employed when forming conductive structures that contact a variety of different semiconductor devices, e.g., transistors, memory cells, resistors, etc., and may be employed when forming conductive structures for a variety of different integrated circuit products, including, but not limited to, ASIC's, logic devices, memory devices, etc. With reference to the attached drawings, various illustrative embodiments of the methods disclosed herein will now be described in more detail.
Formation of the V0 and M1 conductive structures involves formation of a layer of insulating material 118 and an etch mask 119 comprised of first and second layers of material 120, 122. In one example, the layers of insulating material 114, 118 may be layers of so-called low-k (k value less than about 3.3) insulating material, the layer 116 may be a layer of silicon nitride, NBlok, etc., the layer 120 may be a TEOS-based layer of silicon dioxide, and the layer 122 may be a hard mask made of a metal, such as titanium, titanium nitride, etc. The layers of material depicted in
After the cavity 101 is formed, the metal hard mask layer 122 is to be removed.
Formation of the V1 and M2 conductive structures in the metallization layer 133 involves formation of the above-described layer of insulating material 118 and the etch mask 119 comprised of the first and second layers of material 120, 122.
After the cavity 101 is formed, the metal hard mask layer 122 is to be removed.
As should be clear from the foregoing, the novel methods disclosed herein provide an efficient and effective means of forming conductive structures in integrated circuit products that may solve or at least reduce some of the problems identified in the background section of this application. Note that the use of terms such as “first,” “second,” “third” or “fourth” to describe various processes in this specification and in the attached claims is only used as a shorthand reference to such steps and does not necessarily imply that such steps are performed in that ordered sequence. Of course, depending upon the exact claim language, an ordered sequence of such processes may or may not be required.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
Claims
1. A method, comprising:
- forming at least one layer of insulating material above a conductive structure;
- forming a patterned hard mask comprised of metal above said at least one layer of insulating material;
- performing at least one etching process through said patterned hard mask to define a cavity in said at least one layer of insulating material, wherein said cavity exposes at least a portion of said conductive structure;
- forming a layer of sacrificial material so as to overfill said cavity and cover said exposed portion of said conductive structure;
- performing at least one planarization process to remove a portion of said layer of sacrificial material and said patterned hard mask while leaving a remaining portion of said layer of sacrificial material within said cavity; and
- removing said remaining portion of said layer of sacrificial material positioned within said cavity so as to thereby expose said exposed portion of said conductive structure.
2. The method of claim 1, wherein said conductive structure is one of a metal line in a metallization layer or a conductive contact that is conductively coupled to a semiconductor device formed on a semiconductor substrate.
3. The method of claim 1, wherein said conductive structure is comprised of at least one conductive liner layer or a conductive cap layer.
4. The method of claim 1, wherein said at least one layer of insulating material is comprised of silicon dioxide or an insulating material having a k value less than 3.3.
5. The method of claim 1, wherein said patterned hard mask is comprised of at least one of titanium or titanium nitride.
6. The method of claim 1, wherein said layer of sacrificial material is comprised of a flowable oxide material.
7. The method of claim 1, wherein performing at least one planarization process comprises performing a single chemical mechanical polishing process.
8. The method of claim 1, wherein performing at least one planarization process comprises:
- performing a first chemical mechanical polishing process that stops on said patterned hard mask; and
- performing a second chemical mechanical polishing process that stops on or within said at least one layer of insulating material.
9. The method of claim 8, wherein said second chemical mechanical polishing process is a timed chemical mechanical polishing process.
10. The method of claim 1, wherein removing said remaining portion of said layer of sacrificial material positioned within said cavity comprises exposing said remaining portion of said layer of sacrificial material to a dilute HF acid treatment.
11. The method of claim 1, further comprising, after removing said remaining portion of said layer of sacrificial material, forming a second conductive structure in said cavity.
12. A method, comprising:
- forming at least one layer of insulating material having a k value less than 3.3 above a conductive structure;
- forming a patterned hard mask comprised of metal above said at least one layer of insulating material;
- performing at least one etching process through said patterned hard mask to define a cavity in said at least one layer of insulating material, wherein said cavity exposes at least a portion of said conductive structure;
- forming a layer of sacrificial material so as to overfill said cavity and cover said exposed portion of said conductive structure;
- performing at least one chemical mechanical polishing process to remove a portion of said layer of sacrificial material and said patterned hard mask while leaving a remaining portion of said layer of sacrificial material within said cavity; and
- removing said remaining portion of said layer of sacrificial material positioned within said cavity so as to thereby expose said exposed portion of said conductive structure.
13. The method of claim 12, wherein said patterned hard mask is comprised of at least one of titanium or titanium nitride.
14. The method of claim 12, wherein said layer of sacrificial material is comprised of a flowable oxide material.
15. The method of claim 12, wherein removing said remaining portion of said layer of sacrificial material positioned within said cavity comprises exposing said remaining portion of said layer of sacrificial material to a dilute HF acid treatment.
16. The method of claim 12, wherein performing at least one planarization process comprises performing a single chemical mechanical polishing process.
17. The method of claim 12, wherein performing at least one planarization process comprises:
- performing a first chemical mechanical polishing process that stops on said patterned hard mask; and
- performing a second chemical mechanical polishing process that stops on or within said at least one layer of insulating material.
18. The method of claim 17, wherein said second chemical mechanical polishing process is a timed chemical mechanical polishing process.
19. A method, comprising:
- forming at least one layer of insulating material having a k value less than 3.3 above a conductive structure;
- forming a patterned hard mask comprised of metal above said at least one layer of insulating material;
- performing at least one etching process through said patterned hard mask to define a cavity in said at least one layer of insulating material, wherein said cavity exposes at least a portion of said conductive structure;
- forming a layer of sacrificial material comprised of flowable oxide so as to overfill said cavity and cover said exposed portion of said conductive structure;
- performing at least one chemical mechanical polishing process to remove a portion of said layer of sacrificial material and said patterned hard mask while leaving a remaining portion of said layer of sacrificial material within said cavity; and
- removing said remaining portion of said layer of sacrificial material positioned within said cavity so as to thereby expose said exposed portion of said conductive structure.
20. The method of claim 19, wherein said patterned hard mask is comprised of at least one of titanium or titanium nitride.
21. The method of claim 19, wherein removing said remaining portion of said layer of sacrificial material positioned within said cavity comprises exposing said remaining portion of said layer of sacrificial material to a dilute HF acid treatment.
22. The method of claim 19, further comprising, after removing said remaining portion of said sacrificial material layer, forming a second conductive structure in said cavity.
23. The method of claim 19, wherein performing at least one planarization process comprises performing a single chemical mechanical polishing process.
24. The method of claim 19, wherein performing at least one planarization process comprises:
- performing a first chemical mechanical polishing process that stops on said patterned hard mask; and
- performing a second chemical mechanical polishing process that stops on or within said at least one layer of insulating material.
25. The method of claim 24, wherein said second chemical mechanical polishing process is a timed chemical mechanical polishing process.
26. A method, comprising:
- forming at least one layer of insulating material having a k value less than 3.3 above a conductive structure;
- forming a patterned hard mask comprised of titanium or titanium nitride above said at least one layer of insulating material;
- performing at least one etching process through said patterned hard mask to define a cavity in said at least one layer of insulating material, wherein said cavity exposes at least a portion of said conductive structure;
- forming a layer of sacrificial material comprised of flowable oxide so as to overfill said cavity and cover said exposed portion of said conductive structure;
- performing a first chemical mechanical polishing process that stops on said patterned hard mask and removes a portion of said layer of sacrificial material while leaving a remaining portion of said layer of sacrificial material within said cavity;
- performing a second chemical mechanical polishing process that stops on or within said at least one layer of insulating material and removes said patterned hard mask; and
- removing said remaining portion of said layer of sacrificial material positioned within said cavity so as to thereby expose said exposed portion of said conductive structure.
27. The method of claim 26, wherein removing said remaining portion of said layer of sacrificial material positioned within said cavity comprises exposing said remaining portion of said layer of sacrificial material to a dilute HF acid treatment.
28. The method of claim 26, further comprising, after removing said remaining portion of said layer of sacrificial material, forming a second conductive structure in said cavity.
Type: Application
Filed: May 30, 2013
Publication Date: Dec 4, 2014
Applicant: GLOBALFOUNDRIES Inc. (Grand Cayman)
Inventors: Kunaljeet Tanwar (Slingerlands, NY), Xunyuan Zhang (Albany, NY), Xiuyu Cai (Niskayuna, NY)
Application Number: 13/905,271
International Classification: H01L 21/768 (20060101);