Patents by Inventor Xu Ouyang

Xu Ouyang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190284683
    Abstract: An apparatus designed to sputter a material onto a plurality of substrates includes a rotating metal frame, a plurality of carriers, and an insulator disposed between the metal frame and the plurality of carriers. The plurality of carriers are designed to hold one or more fixtures that secure the plurality of substrates, and each of the plurality of carriers is designed to couple to the metal frame. The insulator is disposed between the metal frame and the plurality of carriers at locations where the plurality of carriers are coupled to the metal frame such that the plurality of carriers are electrically isolated from the metal frame.
    Type: Application
    Filed: September 20, 2017
    Publication date: September 19, 2019
    Applicant: CORNING INCORPORATED
    Inventors: Xu Ouyang, Ye Guang Pan
  • Publication number: 20190250144
    Abstract: A nanopore-based sequencing system includes a plurality of nanopore-based sequencing chips. Each of the nanopore-based sequencing chips comprises a plurality of nanopore sensors. The system comprises at least one flow cell coupled to at least one of the plurality of nanopore-based sequencing chips, wherein the flow cell coupled to the at least one of the plurality of nanopore-based sequencing chips comprises one or more fluidic flow channels that allow a fluid external to the system to flow on top of the nanopore-based sequencing chip and out of the system. The system further comprises a printed circuit board electrically connected to the plurality of nanopore-based sequencing chips.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Yuri Mitnick, Xu Ouyang, Janusz B. Wojtowicz
  • Publication number: 20190144942
    Abstract: The present invention provides tools and methods for the systematic analysis of genetic interactions in immune cells. The present invention provides tools and methods for modulating immune cell phenotypes and compositions, combinatorial probing of cellular circuits, for dissecting cellular circuitry, for delineating molecular pathways, and/or for identifying relevant targets for therapeutics development.
    Type: Application
    Filed: February 22, 2017
    Publication date: May 16, 2019
    Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE GENERAL HOSPITAL CORPORATION
    Inventors: Alexander K. SHALEK, Kellie E. KOLB, Michael B. COLE, Nir YOSEF, Enrique Martin GAYO, Zhengyu OUYANG, Xu YU
  • Patent number: 10156605
    Abstract: An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: December 18, 2018
    Assignee: Semitronix Corporation
    Inventors: Weiwei Pan, Yongli Liu, Xu Ouyang, Yongjun Zheng, Zheng Shi, Lili Li
  • Patent number: 10077207
    Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 18, 2018
    Assignee: Corning Incorporated
    Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
  • Publication number: 20180230589
    Abstract: A process in which both an optical coating, for example, an AR coating, and an ETC coating are deposited on a glass substrate article, in sequential steps, with the optical coating being deposited first and the ETC coating being deposited second, using the same apparatus and without exposing the article to the atmosphere at any time during the application of the optical coating and ETC coating.
    Type: Application
    Filed: April 11, 2018
    Publication date: August 16, 2018
    Inventors: Christopher Morton Lee, Xiao-Feng Lu, Xu Ouyang, Junhong Zhang
  • Patent number: 9957609
    Abstract: A process in which both an optical coating, for example, an AR coating, and an ETC coating are deposited on a glass substrate article, in sequential steps, with the optical coating being deposited first and the ETC coating being deposited second, using the same apparatus and without exposing the article to the atmosphere at any time during the application of the optical coating and ETC coating.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: May 1, 2018
    Assignee: CORNING INCORPORATED
    Inventors: Christopher Morton Lee, Xiao-feng Lu, Xu Ouyang, Junhong Zhang
  • Patent number: 9780007
    Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
  • Patent number: 9646900
    Abstract: A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the scribe lines or a pre-allocated area of the wafer. When testing the target chip, a circuit connecting the target chip and the addressing circuits can be fabricated on demand. In some cases the target chip is not connected to the addressing circuits, and a DUT array exists in a scribe line having a connecting circuit prefabricated between the addressing circuits with the DUT array for testing the DUT array in the scribe line. When the need for testing the target chip arises, the prefabricated connecting circuit can be cut, and the connecting circuit connecting the target chip and the addressing circuits can be fabricated. Based on results from such test chips, the manufacturing process can be better studied.
    Type: Grant
    Filed: January 24, 2015
    Date of Patent: May 9, 2017
    Assignee: Semitronix Corporation
    Inventors: Xu Ouyang, Yongjun Zheng, Zheng Shi, Peiyong Zhang
  • Publication number: 20160061895
    Abstract: An addressable ring oscillator test chip includes: a plurality of ring oscillator test units, and a peripheral structure including peripheral circuits and PADs. The peripheral circuits share a first power source and a first grounding. Each test unit is associated with an independent power source to thereby decrease voltage drop resulting from wiring and to reduce the influence from other test units. A method of generating a variety of ring oscillators includes: generating a cell template corresponding to a basic unit, including defining a parameterized cell template; generating a ring oscillator based on the cell template, including generating ring oscillators of different stages by selecting different parameters of the cell template; realizing internal connections of the ring oscillator; and generating an instantiated ring oscillator by replacing cell templates with corresponding basic units.
    Type: Application
    Filed: August 20, 2015
    Publication date: March 3, 2016
    Inventors: Weiwei Pan, Yongli Liu, Xu Ouyang, Yongjun Zheng, Zheng Shi, Lili Li
  • Publication number: 20150322270
    Abstract: Embodiments of durable, anti-reflective articles are described. In one or more embodiments, the article includes a substrate and an anti-reflective coating disposed on the major surface. The article exhibits an average light transmittance of about 94% or greater over an optical wavelength regime and/or an average light reflectance of about 2% or less over the optical wavelength regime, as measured from an anti-reflective surface. In some embodiments, the article exhibits a maximum hardness of about 8 GPa or greater as measured by a Berkovich Indenter Hardness Test along an indentation depth of about 50 nm or greater and a b* value, in reflectance, in the range from about ?5 to about 1 as measured on the anti-reflective surface only at all incidence illumination angles in the range from about 0 degrees to about 60 degrees under an International Commission on Illumination illuminant.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 12, 2015
    Inventors: Jaymin Amin, Shandon Dee Hart, Karl William Koch, III, Eric Louis Null, Xu Ouyang, Charles Andrew Paulson, James Joseph Price
  • Patent number: 9146270
    Abstract: The present invention relates to the chip testing field. A method for testing a plurality of transistors in a target chip is provided, characterized by automatically selecting a plurality of pre-defined transistors on the target chip and adding a connection layer to the key layers of each transistor such that the transistor to be tested is connected with and measured by an outside tester. Through automatic generation of the test structures and automatic wiring, the present invention greatly shortens the design cycle of test chips for target transistor testing, and greatly reduces the error probability in the process of designing test chips for target transistor testing, and improves the testing relevancy.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: September 29, 2015
    Assignee: SEMITRONIX CORPORATION
    Inventors: Kangpeng Shao, Yongjun Zheng, Xu Ouyang
  • Publication number: 20150212144
    Abstract: A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the scribe lines or a pre-allocated area of the wafer. When testing the target chip, a circuit connecting the target chip and the addressing circuits can be fabricated on demand. In some cases the target chip is not connected to the addressing circuits, and a DUT array exists in a scribe line having a connecting circuit prefabricated between the addressing circuits with the DUT array for testing the DUT array in the scribe line. When the need for testing the target chip arises, the prefabricated connecting circuit can be cut, and the connecting circuit connecting the target chip and the addressing circuits can be fabricated. Based on results from such test chips, the manufacturing process can be better studied.
    Type: Application
    Filed: January 24, 2015
    Publication date: July 30, 2015
    Inventors: XU OUYANG, YONGJUN ZHENG, ZHENG SHI, PEIYONG ZHANG
  • Patent number: 9013795
    Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: April 21, 2015
    Assignee: Corning Incorporated
    Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
  • Publication number: 20150015959
    Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.
    Type: Application
    Filed: July 29, 2014
    Publication date: January 15, 2015
    Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
  • Publication number: 20150002184
    Abstract: The present invention relates to the chip testing field. A method for testing a plurality of transistors in a target chip is provided, characterized by automatically selecting a plurality of pre-defined transistors on the target chip and adding a connection layer to the key layers of each transistor such that the transistor to be tested is connected with and measured by an outside tester. Through automatic generation of the test structures and automatic wiring, the present invention greatly shortens the design cycle of test chips for target transistor testing, and greatly reduces the error probability in the process of designing test chips for target transistor testing, and improves the testing relevancy.
    Type: Application
    Filed: February 11, 2014
    Publication date: January 1, 2015
    Applicant: Semitronix Corporation
    Inventors: Kangpeng Shao, Yongjun Zheng, Xu Ouyang
  • Patent number: 8817376
    Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: August 26, 2014
    Assignee: Corning Incorporated
    Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
  • Patent number: 8790989
    Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: July 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Xu Ouyang, Chih-Chao Yang
  • Patent number: 8759175
    Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang
  • Patent number: 8742782
    Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin