Patents by Inventor Xu Ouyang
Xu Ouyang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8742782Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: GrantFiled: July 27, 2011Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Publication number: 20140016201Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.Type: ApplicationFiled: September 10, 2013Publication date: January 16, 2014Applicant: CORNING INCORPORATEDInventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
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Patent number: 8619365Abstract: Multilayer anti-reflective coatings having four or more layers are disclosed. In one aspect, the multilayer anti-reflective coating comprises a first layer having a refractive index n1, where n1<1.4, and an optical thickness of (0.25±5%) ?o nm; a second layer adjacent to the first layer, the second layer having a refractive index n2, where n2?1.8, and an optical thickness of (0.5±5%) ?o nm; a third layer adjacent to the second layer, the third layer having a refractive index n3, where 1.4?n3<1.6, and an optical thickness of (0.1±5%) ?o nm; and a fourth layer adjacent to the third layer, the fourth layer having a refractive index n4, where n4?1.8, and an optical thickness of (0.05±10%) ?o nm; where ?o is a wavelength in the visible light range.Type: GrantFiled: October 8, 2009Date of Patent: December 31, 2013Assignee: Corning IncorporatedInventors: Michael David Harris, Christopher Morton Lee, Lawrence George Mann, Mike Xu Ouyang
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Publication number: 20130334031Abstract: A process in which both an optical coating, for example, an AR coating, and an ETC coating are deposited on a glass substrate article, in sequential steps, with the optical coating being deposited first and the ETC coating being deposited second, using the same apparatus and without exposing the article to the atmosphere at any time during the application of the optical coating and ETC coating.Type: ApplicationFiled: May 30, 2013Publication date: December 19, 2013Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
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Publication number: 20130263784Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.Type: ApplicationFiled: May 30, 2013Publication date: October 10, 2013Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
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Publication number: 20130260530Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.Type: ApplicationFiled: May 30, 2013Publication date: October 3, 2013Applicant: International Business Machines CorporationInventors: Louis L. Hsu, Xu Ouyang, Chih-Chao Yang
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Patent number: 8487696Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.Type: GrantFiled: April 3, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Xu Ouyang, Chih-Chao Yang
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Patent number: 8489225Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer. The optical coherence tomography system is configured and disposed to compute coordinate data for a plurality of alignment marks on the first wafer and second wafer, and send that coordinate data to the wafer alignment system.Type: GrantFiled: March 8, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Yongchun Xin, Xu Ouyang, Yunsheng Song, Tso-Hui Ting
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Publication number: 20130169308Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
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Publication number: 20130135741Abstract: This disclosure is directed to an improved process for making glass articles having optical coating and easy-to clean coating thereon, an apparatus for the process and a product made using the process. In particular, the disclosure is directed to a process in which the application of the optical coating and the easy-to-clean coating can be sequentially applied using a single apparatus. Using the combination of the coating apparatus and the substrate carrier described herein results in a glass article having both optical and easy-to-clean coating that have improved scratch resistance durability and optical performance, and in addition the resulting articles are “shadow free.Type: ApplicationFiled: November 30, 2012Publication date: May 30, 2013Inventors: Christopher Morton Lee, Xiao-feng Lu, Michael Xu Ouyang, Junhong Zhang
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Patent number: 8369976Abstract: A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots from tool to tool in a manner which at least partially neutralizes or compensates for processing variations. A system for increasing overall yield in semiconductor manufacturing includes a module for recording processing data from plural first and second types of tools and a module for routing wafers or wafer lots from tools of the first type of tools to tools of the second type of tools so as to at least partially neutralizes or compensate for processing variation.Type: GrantFiled: June 23, 2008Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Keith Kwong Hon Wong, Xu Ouyang, Yunsheng Song
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Publication number: 20130027051Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.Type: ApplicationFiled: July 27, 2011Publication date: January 31, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin
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Publication number: 20130016895Abstract: A system and method for fail pattern analysis for a memory device is disclosed. The peripheral circuits of a memory device are divided into different zones based on circuit design and layout. Defects are detected by inline inspection of multiple SRAM devices at various stages in the manufacturing process and saved into a database. When the devices are fabricated, electrical tests are then performed. Electrical failure patterns are also recorded and saved in the database. A correlation between the zone in which a visual defect resides and an electrical failure is recorded in computer storage. Visual defects found during inline inspection are then associated with an electrical failure in the memory device.Type: ApplicationFiled: July 15, 2011Publication date: January 17, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhigang Song, Xu Ouyang, Yunsheng Song
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Patent number: 8347246Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.Type: GrantFiled: March 30, 2012Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Xu Ouyang, Geng Han, Lars W. Liebmann
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Patent number: 8339893Abstract: A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.Type: GrantFiled: September 25, 2009Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Louis C. Hsu, Xu Ouyang, Robert C. Wong
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Patent number: 8294485Abstract: A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifest themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. Leakage is measured by applying an appropriate off-state voltage (e.g., 0V) by a common connection to all of the gates of the transistors in the test array, then measuring the aggregate drain/source leakage current, both forward and reverse (e.g., first grounded source and positively biased drain, then grounded drain and positively biased source) comparing the difference between the two leakage current measurements.Type: GrantFiled: February 3, 2010Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Xu Ouyang, Yun-Yu Wang, Yunsheng Song
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Publication number: 20120232686Abstract: A system for performing alignment of two wafers is disclosed. The system comprises an optical coherence tomography system and a wafer alignment system. The wafer alignment system is configured and disposed to control the relative position of a first wafer and a second wafer.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: International Business Machines CorporationInventors: Yongchun Xin, Xu Ouyang, Yunsheng Song, Tso-Hui Ting
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Publication number: 20120188002Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. Hsu, Xu Ouyang, Chih-Chao Yang
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Publication number: 20120192137Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Geng Han, Lars W. Liebmann
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Publication number: 20120184076Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis C. Hsu, Xu Ouyang, Ping-Chuan Wang, Zhijian J. Yang