Abstract: A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells.

Abstract: Methods and apparatus provide for: disposing an intermediate layer formed from at least one of: a metal, a conductive oxide, and combined layers of the metal and the conductive oxide, on one of a first material layer and a second material layer; and coupling the first and second material layers together via an anodic bond between the intermediate layer and the other of the first and second material layers.

Abstract: A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract: A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The inspection points are located by identifying at least one fiducial that corresponds to an X-Y offset from the desired inspection point. The fiducials are recognized by a computer vision system. By automating the inspection process, the time required to perform the inspections is greatly reduced.

Abstract: A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

Abstract: A method for increasing overall yield in semiconductor manufacturing including routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from tools processing the wafers or wafer lots. A system for increasing overall yield in semiconductor manufacturing includes a module for routing wafers or wafer lots based on process variation data obtained from the wafers or wafer lots and on process variation data obtained from the tools processing the wafers or wafer lots.

Abstract: A semiconductor device includes a SRAM having a pair of MCSFETs connected as access transistors (pass gates). A design structure embodied or stored in a machine readable medium includes a SRAM having two MCSFETs connected as access transistors.

Abstract: A method for optimizing multiple process windows in a semiconductor manufacturing process is disclosed. The method comprises performing dependent variable composition on a plurality of dependent variables. Metrology data is joined with the dependent variables, and then a partial least squares regression is performed on the joined data set to obtain a prediction equation, and a variable importance prediction for each process window in a process window set. A set of product limited yield are derived, and the process window, set is adjusted, and the yields recalculated, until an optimal process window set is derived.

Abstract: Excluding variations attributable to equipment from split analysis is performed by identifying dependent variables related to at least one of the split analysis or an experiment to be performed. A test is performed to ascertain whether or not a variation attributable to equipment exists with respect to any of the identified dependent variables. If such a variation exists, a target data set and a training data set are constructed. A signature is identified for the variation. A statistical model is selected based upon the identified signature. The selected statistical model is constructed using the training data set to generate a statistical output. The target data set is joined with the statistical output. The identified dependent variables in the target data set are adjusted using the statistical output. The target data set including the adjusted identified dependent variables is loaded to an application for performing split analysis.

Abstract: A method of failure detection of an integrated circuit (IC) layout includes determining a critical path distance between a first geometric feature of the IC layout and a second geometric feature of the IC layout; and comparing the determined critical path distance to a defined minimum critical path distance between the first and second geometric features, wherein the defined minimum critical path distance corresponds to a desired electrical property of the IC layout, independent of any geometric-based ground rule minimum distance for the IC layout; identifying any determined critical path distances that are less than the defined minimum critical path distance as a design violation; and modifying the IC layout by eliminating the identified design violations.

Abstract: A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

Abstract: A method of detecting low-probability defects in large transistor arrays (such as large arrays of SRAM cells), where the defects manifesting themselves as asymmetrical leakage in a transistor (such as a pulldown nFET in an SRAM cell). These defects are detected by creating one or more test arrays, identical in all regards to the large transistor arrays up until the contact and metallization layers. The test array(s) is (are) disposed side-by-side with the “normal” array(s) on the same reticle so that process variations that affect the normal array will also affect the test array. The contact and metallization layers for the test array are adapted to connect groups (sub-blocks) of transistors together in parallel for leakage testing. The group size is chosen to ensure that the leakage current associated with a single defective transistor is significantly greater than the aggregate leakage current associated with all of non-defective transistors in the group.

Abstract: A system and method for failure analysis of devices on a semiconductor wafer is disclosed. The present invention comprises the use of an inline focused ion beam milling tool to perform milling and image capturing of cross sections of a desired inspection point. The inspection points are located by identifying at least one fiducial that corresponds to an X-Y offset from the desired inspection point. The fiducials are recognized by a computer vision system. By automating the inspection process, the time required to perform the inspections is greatly reduced.

Abstract: A process for making a MCSFET includes providing a first implant through a first side of an elongated stack, and then providing a second implant through a second side of the stack. The first implant has a dose different than the dose of the second implant, so that final dopant concentrations in the first and second sides differ and the transistor has two threshold voltages Vt1, Vt2.

Abstract: A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

Abstract: Multilayer anti-reflective coatings having four or more layers are disclosed. In one aspect, the multilayer anti-reflective coating comprises a first layer having a refractive index n1, where n1<1.4, and an optical thickness of (0.25±5%) ?o nm; a second layer adjacent to the first layer, the second layer having a refractive index n2, where n2?1.8, and an optical thickness of (0.5±5%) ?o nm; a third layer adjacent to the second layer, the third layer having a refractive index n3, where 1.4?n3<1.6, and an optical thickness of (0.1±5%) ?o nm; and a fourth layer adjacent to the third layer, the fourth layer having a refractive index n4, where n4?1.8, and an optical thickness of (0.05±10%) ?o nm; where ?o is a wavelength in the visible light range.