Patents by Inventor Xun Xue

Xun Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TWO-LEVEL MANAGEMENT OF LOCKS ON SHARED RESOURCES
    Publication number: 20150019739
    Abstract: In a shared data system comprising one or more primary nodes and a plurality of secondary nodes, global lock manager on a primary node manages locks for shared resources by exchanging an abstract lock state with local lock managers on the secondary nodes. The abstract lock state includes a particular representation of all of the applications on the nodes that are requesting or are granted locks. The exchange of these particular lock states instead of individual requests improves performance by increasing concurrency and reducing off-machine communication. A global deadlock detector on a node detects and resolves global deadlocks, in conjunction with local deadlock detectors on the secondary nodes.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 15, 2015
    Inventors: Gopi K. Attaluri, James L. Finnie, Stewart L. Palmer, Piotr M. Plachta, Garret F. Swart, Xun Xue, Roger L.Q. Zheng
  • Stacked power semiconductor device using dual lead frame
    Patent number: 8933518
    Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
  • Double-side exposed semiconductor device
    Patent number: 8933545
    Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yuping Gong, Yan Xun Xue
  • Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors
    Patent number: 8933550
    Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Anup Bhalla, Jun Lu
  • WAFER LEVEL CHIP SCALE PACKAGE WITH EXPOSED THICK BOTTOM METAL
    Publication number: 20150001686
    Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.
    Type: Application
    Filed: September 8, 2014
    Publication date: January 1, 2015
    Inventor: Yan Xun Xue
  • A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET
    Publication number: 20140361418
    Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu
  • POWER CONTROL DEVICE AND PREPARATION METHOD THEREOF
    Publication number: 20140361419
    Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Yan Xun Xue, Hamza Yilmaz
  • HYBRID PACKAGING MULTI-CHIP SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF
    Publication number: 20140361420
    Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
  • Wafer level chip scale package
    Patent number: 8890296
    Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yueh-Se Ho, Yan Xun Xue
  • Flip-chip semiconductor chip packing method
    Patent number: 8877555
    Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Lei Shi, Yan Xun Xue, Yuping Gong
  • BOTTOM SOURCE SUBSTRATELESS POWER MOSFET
    Publication number: 20140319601
    Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Inventors: Yueh-Se Ho, Yan Xun Xue, Ping Huang
  • WAFER PROCESS FOR MOLDED CHIP SCALE PACKAGE (MCSP) WITH THICK BACKSIDE METALLIZATION
    Publication number: 20140315350
    Abstract: A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, Zhiqiang Niu, Guo Feng Lian, Hong Xia Fu, Yu Ping Gong
  • DOUBLE-SIDE EXPOSED SEMICONDUCTOR DEVICE
    Publication number: 20140312480
    Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.
    Type: Application
    Filed: April 18, 2013
    Publication date: October 23, 2014
    Inventors: Yuping Gong, Van Xun Xue
  • Semiconductor package and fabrication method thereof
    Patent number: 8865523
    Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Two-level management of locks on shared resources
    Patent number: 8868755
    Abstract: In a shared data system comprising one or more primary nodes and a plurality of secondary nodes, global lock manager on a primary node manages locks for shared resources by exchanging an abstract lock state with local lock managers on the secondary nodes. The abstract lock state includes a particular representation of all of the applications on the nodes that are requesting or are granted locks. The exchange of these particular lock states instead of individual requests improves performance by increasing concurrency and reducing off-machine communication. A global deadlock detector on a node detects and resolves global deadlocks, in conjunction with local deadlock detectors on the secondary nodes.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gopi K. Attaluri, James L. Finnie, Stewart L. Palmer, Piotr M. Plachta, Garret F. Swart, Xun Xue, Roger L.Q. Zheng
  • Two-level management of locks on shared resources
    Patent number: 8868748
    Abstract: In a shared data system comprising one or more primary nodes and a plurality of secondary nodes, global lock manager on a primary node manages locks for shared resources by exchanging an abstract lock state with local lock managers on the secondary nodes. The abstract lock state includes a particular representation of all of the applications on the nodes that are requesting or are granted locks. The exchange of these particular lock states instead of individual requests improves performance by increasing concurrency and reducing off-machine communication. A global deadlock detector on a node detects and resolves global deadlocks, in conjunction with local deadlock detectors on the secondary nodes.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gopi K. Attaluri, James L. Finnie, Stewart L. Palmer, Piotr M. Plachta, Garret F. Swart, Xun Xue, Roger L. Q. Zheng
  • Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
    Patent number: 8853003
    Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.
    Type: Grant
    Filed: September 1, 2012
    Date of Patent: October 7, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: Yan Xun Xue
  • Manufacturing method of a semiconductor package of small footprint with a stack of lead frame die paddle sandwiched between high-side and low-side MOSFET
    Patent number: 8841167
    Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yuping Gong, Yan Xun Xue, Liang Zhao
  • Semiconductor Device with Thick Bottom Metal and Preparation Method Thereof
    Publication number: 20140264802
    Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Ming-Chen Lu, Yan Huo, Aihua Lu
  • Semiconductor Package And Fabrication Method Thereof
    Publication number: 20140264805
    Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao, Ping Huang