Patents by Inventor Xun Xue

Xun Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194347
    Abstract: A semiconductor package has a plurality of pillars or portions of a plurality of lead strips, a plurality of semiconductor devices, one or two molding encapsulations and a plurality of electrical interconnections. The semiconductor package excludes a wire. The semiconductor package excludes a clip. A method is applied to fabricate semiconductor packages. The method includes providing a removable carrier; forming a plurality of pillars or a plurality of lead strips; attaching a plurality of semiconductor devices; forming one or two molding encapsulations; forming a plurality of electrical interconnections and removing the removable carrier. The method may further include a singulation process.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 18, 2020
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Xiaotian Zhang, Long-Ching Wang, Yueh-Se Ho, Zhiqiang Niu
  • Publication number: 20200159845
    Abstract: Methods and systems are described for managing a shared database. One or more processing nodes may access a shared database. A common log node may manage the shared database. The common log node may validate database operations requested by the one or more processing nodes. During validation, the common log node may detect conflicts that occur between database operations requested by the one or more processing nodes.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xun XUE, Chong CHEN, Per-Ake LARSON, Robin GROSMAN
  • Publication number: 20190384754
    Abstract: A method includes storing an anchor row vector identification for an anchor row to a local memory. It is determined whether the anchor row vector identification is visible based on isolation requirements. The anchor row vector identification is accessed upon a determination that the anchor row vector identification is visible, and the row vector identification is re-read from the local memory. It is determined whether the anchor row vector identification has not changed since a start of the accessing. Upon a determination that the anchor row vector identification has not changed, read anchor row fields are returned. A first check history is performed on an anchor row history tuple sequence number (TSN) for the anchor row.
    Type: Application
    Filed: August 29, 2019
    Publication date: December 19, 2019
    Inventors: Ronald J. Barber, Bishwaranjan Bhattacharjee, Mohammad Sadoghi Hamedani, Guy M. Lohman, Chandrasekaran Mohan, Vijayshankar Raman, Richard S. Sidle, Adam J. Storm, Xun Xue
  • Patent number: 10489374
    Abstract: A method includes setting, by an update processor, a write latch in a first data structure associated with an object. The first data structure is copied to a storage structure. A history tuple sequence number (TSN) of the first data structure is set to point to a TSN of the copied first data structure. The version identifier is set to point to a transaction identification for the object. Data portions are updated for the first data structure. The version identifier is read from the first data structure. It is determined whether the version identifier of the first data structure is visible for a transaction including isolation requirements. If version identifier of the first data structure is visible, the first data structure is accessed and it is determined whether the version identifier of the first data structure changed since starting the transaction.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Barber, Bishwaranjan Bhattacharjee, Mohammad Sadoghi Hamedani, Guy M. Lohman, Chandrasekaran Mohan, Vijayshankar Raman, Richard S. Sidle, Adam J. Storm, Xun Xue
  • Patent number: 10141264
    Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 27, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventor: Yan Xun Xue
  • Patent number: 10083203
    Abstract: A first request may be received to update a first set of values. The first set of values may be stored at a first location within a first data page of a database. The first location may be read-only. In response to the receiving of the first request, a first set of records may be inserted into a second data page. The first set of records may include the update of the first set of values. In response to the inserting, a forward pointer may be stored in the first data page that points to the first set of records on the second data page. One or more committed values may be identified on the second data page. In response to the identifying, the one or more committed values may be merged from the second data page to a third data page.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Barber, Bishwaranjan Bhattacharjee, Guy M. Lohman, Chandrasekaran Mohan, Vijayshankar Raman, Mohammad Sadoghi Hamedani, Richard S. Sidle, Adam J. Storm, Xun Xue
  • Patent number: 10043736
    Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: August 7, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
  • Publication number: 20180211916
    Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
    Type: Application
    Filed: March 21, 2018
    Publication date: July 26, 2018
    Inventor: Yan Xun Xue
  • Patent number: 9966328
    Abstract: A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method for fabricating semiconductor power devices.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 8, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yan Xun Xue, Zhiqiang Niu
  • Patent number: 9960119
    Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 1, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Yan Xun Xue
  • Publication number: 20180101558
    Abstract: Techniques for data replication from a primary system to a standby system. A first buffer portion of a transaction log buffer is allocated to a first transaction at a primary system. Upon determining that the first buffer portion is fully formed, before the log data is written to the storage on the primary system, and before the transaction log buffer is entirely full, the log data in the first buffer portion is transmitted to the standby system, from the primary system. Upon writing the log data to the storage on the primary system and after the log data in the first buffer portion is transmitted to the standby system, a notification is transmitted to the standby system, from the primary system, where the standby system is configured to process the received log data responsive to receiving the notification from the primary system.
    Type: Application
    Filed: December 4, 2017
    Publication date: April 12, 2018
    Inventors: Xun Xue, Steven R. Pearson, Roger L.Q. Zheng, Kevin J. Cherkauer
  • Patent number: 9940346
    Abstract: In a shared data system comprising one or more primary nodes and a plurality of secondary nodes, global lock manager on a primary node manages locks for shared resources by exchanging an abstract lock state with local lock managers on the secondary nodes. The abstract lock state includes a particular representation of all of the applications on the nodes that are requesting or are granted locks. The exchange of these particular lock states instead of individual requests improves performance by increasing concurrency and reducing off-machine communication. A global deadlock detector on a node detects and resolves global deadlocks, in conjunction with local deadlock detectors on the secondary nodes.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gopi K. Attaluri, James L. Finnie, Stewart L. Palmer, Piotr M. Plachta, Garret F. Swart, Xun Xue, Roger L. Q. Zheng
  • Patent number: 9929076
    Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: March 27, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu
  • Patent number: 9922077
    Abstract: A first request may be received to update a first set of values. The first set of values may be stored at a first location within a first data page of a database. The first location may be read-only. In response to the receiving of the first request, a first set of records may be inserted into a second data page. The first set of records may include the update of the first set of values. In response to the inserting, a forward pointer may be stored in the first data page that points to the first set of records on the second data page. One or more committed values may be identified on the second data page. In response to the identifying, the one or more committed values may be merged from the second data page to a third data page.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Barber, Bishwaranjan Bhattacharjee, Guy M. Lohman, Chandrasekaran Mohan, Vijayshankar Raman, Mohammad Sadoghi Hamedani, Richard S. Sidle, Adam J. Storm, Xun Xue
  • Patent number: 9881049
    Abstract: A first request may be received to update a first set of values. The first set of values may be stored at a first location within a first data page of a database. The first location may be read-only. In response to the receiving of the first request, a first set of records may be inserted into a second data page. The first set of records may include the update of the first set of values. In response to the inserting, a forward pointer may be stored in the first data page that points to the first set of records on the second data page. One or more committed values may be identified on the second data page. In response to the identifying, the one or more committed values may be merged from the second data page to a third data page.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ronald J. Barber, Bishwaranjan Bhattacharjee, Guy M. Lohman, Chandrasekaran Mohan, Vijayshankar Raman, Mohammad Sadoghi Hamedani, Richard S. Sidle, Adam J. Storm, Xun Xue
  • Patent number: 9864772
    Abstract: Methods, systems and program products for log-shipping data replication from a primary system to a communicatively-coupled standby system. Embodiments of the invention may receive transactional log data at a standby system, from the primary system, and before the transactional log data is written to storage on the primary system. Embodiments may then receive a notification from the primary system indicating that the corresponding log data was written to storage on the primary system, and responsive to receiving the notification, may process the received transactional log data.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kevin J. Cherkauer, Steven R. Pearson, Xun Xue, Roger L. Q. Zheng
  • Publication number: 20170372987
    Abstract: A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or more semiconductor chip stacks, and a molding encapsulation. Each semiconductor chip stack includes a high-side semiconductor chip, a low-side semiconductor chip and a clip connecting a top surface of the high-side semiconductor chip to a bottom surface of the low-side semiconductor chip. This invention further discloses a method for fabricating semiconductor power devices.
    Type: Application
    Filed: July 25, 2017
    Publication date: December 28, 2017
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Zhiqiang Niu
  • Patent number: 9854686
    Abstract: A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: December 26, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
  • Patent number: 9786583
    Abstract: A power semiconductor package device and a method of preparation the device are disclosed. The package device includes a die paddle, a first pin, a second pin, and a semiconductor chip attached to the die paddle. A first electrode, a second electrode and a third electrode of the semiconductor chip are connected to the first pin, the second pin and the die paddle respectively. A plastic package body covers the semiconductor chip, the die paddle, the first pin and the second pin. The first pin and the second pin are located near two adjacent corners of the plastic package body. The bottom surface and two side surfaces of each of the first pin and the second pin are exposed from the plastic package body. Locking mechanisms are constructed to prevent the first pin and the second pin from falling off the power semiconductor package device during a manufacturing cutting process. Portions of the first pin, portions of the second pin, and portions of the plastic package body can be cut off.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 10, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yan Xun Xue, Hamza Yilmaz, Yueh-Se Ho, Jun Lu, De Mei Gong
  • Patent number: 9768146
    Abstract: The present invention discloses small-size battery protection packages and provides a process of fabricating small-size battery protection packages. A battery protection package includes a first common-drain metal oxide semiconductor field effect transistor (MOSFET), a second common-drain MOSFET, a power control integrated circuit (IC), a plurality of solder balls, a plurality of conductive bumps, and a packaging layer. The power control IC is vertically stacked on top of the first and second common-drain MOSFETs. At least a majority portion of the power control IC and at least majority portions of the plurality of solder balls are embedded into the packaging layer.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 19, 2017
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Zhiqiang Niu, Yan Xun Xue, Man Sheng Hu, Jun Lu, Yueh-Se Ho, Hamza Yilmaz