Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.

Abstract: A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles arranged side by side, a first semiconductor chip attached to the first die paddle, a second semiconductor chip attached to the second die paddle, a metal clip electrically connecting a first electrode at the top surface of the first semiconductor chip and a first electrode at the top surface of the second semiconductor chip to a second pin, a first conductive structure connecting a second electrode at the top surface of a first semiconductor chip to a first pin, and a second conductive structure connecting a second electrode at the top surface of the second semiconductor chip to a third pin. In examples of the present disclosure, double-chip common source technique for the source electrodes of two power MOSFETs is achieved by applying a T-shape metal clip.

Abstract: A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines.

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

Abstract: A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.

Abstract: An ordering of operations in log records includes: performing update operations on a database object by a node; writing log records for the update operations into a local buffer by the node, the log records each including a local virtual timestamp; determining that a log flush to write the log records in the local buffer to a persistent storage is to be performed; in response, sending a request from the node to a log flush sequence server for a log flush sequence number; receiving the log flush sequence number by the node; inserting the log flush sequence number into the log records in the local buffer; and performing the log flush to write the log records in the local buffer to the persistent storage, where the log records written to the persistent storage comprises the local virtual timestamps and the log flush sequence number.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.

Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.

Abstract: The present invention is directed to a lead-frame having a stack of semiconductor dies with interposed metalized clip structure. Level projections extend from the clip structure to ensure that the clip structure remains level during fabrication.

Abstract: According to embodiments of the present invention, one or more computer processors determine that a predetermined workload threshold associated with an invalidated object is not exceeded and transmits an invalidation command associated with the invalidated object to the owner of the invalidated object. The one or more computer processors instruct the modifier of the invalidated object to retain possession of a first lock on the object beyond the transaction. The one or more computer processors determine that a usage pattern associated with the invalidated object matches a predetermined usage pattern for selecting a lock that can be retained beyond an associated transaction and transmits a second lock a requestor. The one or more computer processors instruct the modifier to release possession of the first lock to the owner and transmit a first image of the current version of the invalidated object to the owner for subsequent transmission to the requestor.

Abstract: According to embodiments of the present invention, one or more computer processors determine that a predetermined workload threshold associated with an invalidated object is not exceeded and transmits an invalidation command associated with the invalidated object to the owner of the invalidated object. The one or more computer processors instruct the modifier of the invalidated object to retain possession of a first lock on the object beyond the transaction. The one or more computer processors determine that a usage pattern associated with the invalidated object matches a predetermined usage pattern for selecting a lock that can be retained beyond an associated transaction and transmits a second lock a requestor. The one or more computer processors instruct the modifier to release possession of the first lock to the owner and transmit a first image of the current version of the invalidated object to the owner for subsequent transmission to the requestor.