Abstract: At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

Abstract: One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, forming a non-uniform thickness layer of material on the upper surface of the gate cap layers and on the upper surface of the source/drain contact structure, wherein the non-uniform thickness layer of material is thicker above the gate cap layers than it is above the source/drain contact structure, forming an opening in the non-uniform thickness layer of material so as to expose at least a portion of the source/drain contact structure, and forming a V0 via that is conductively coupled to the exposed portion of the source/drain contact structure, the V0 via being at least partially positioned in the opening in the non-uniform thickness layer of material.

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract: One method disclosed herein includes, among other things, performing a process operation on an exposed surface of a substrate so as to form an H-terminated silicon surface, selectively forming a sacrificial material layer within a replacement gate cavity but not on the H-terminated silicon surface, forming a high-k layer of insulating material within the replacement gate cavity above the H-terminated silicon surface and laterally between first spaced-apart portions of the sacrificial material layer, and forming a work-function adjusting material layer in the gate cavity, wherein the work-function adjusting material layer has a substantially planar upper surface that extends between second spaced-apart portions of the sacrificial material layer formed on the sidewall spacers.

Abstract: One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, recessing the source/drain contact structure to define a source/drain contact etch cavity and depositing a conformal second layer of insulating material above a first layer of insulating material and in the source/drain contact etch cavity. The method also includes forming a third layer of insulating material above the conformal second layer of insulating material, forming an opening in the conformal second layer of insulating material and forming a V0 via that is conductively coupled to the exposed portion of the recessed source/drain contact structure.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.

Abstract: A method of fabricating raised fin structures is provided, the fabricating including: providing a substrate and at least one dielectric layer over the substrate; forming a trench in the at least one dielectric layer, the trench having a lower portion, a lateral portion, and an upper portion, the upper portion being at least partially laterally offset from the lower portion and being joined to the lower portion by the lateral portion; and, growing a material in the trench to form the raised fin structure, wherein the trench is formed to ensure that any growth defect in the lower portion of the trench terminates either in the lower portion or the lateral portion of the trench and does not extend into the upper portion of the trench.

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.

Abstract: One illustrative method disclosed herein includes, among other things, performing at least one etching process through an overall masking layer to define an opening in a layer of insulating material, wherein the overall masking layer is comprised of a patterned metal-silicate masking layer that is positioned on and in contact with the layer of insulating material and a patterned masking layer positioned on and in contact with the patterned metal-silicate masking layer, over-filling the opening with a conductive material and performing at least one planarization process so as to remove excess materials positioned outside of the opening above the patterned metal-silicate masking layer and thereby define a conductive structure that is positioned in the opening.

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in at least one layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective metal silicide formation process to selectively form a metal silicide layer in the opening and on the conductive contact, depositing at least one conductive material above the selectively formed metal silicide layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials and thereby define a conductive via that is positioned in the opening and conductively coupled to the selectively formed metal silicide layer and to the conductive contact.

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.

Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

Abstract: Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon. The integrated circuit includes a contact structure in electrical contact with the device. The contact structure includes a plug metal and a barrier layer, and the barrier layer is selected from fluorine-free tungsten (FFW), tungsten carbide, and tungsten nitride. The integrated circuit further includes a dielectric material overlying the semiconductor substrate. Also, the integrated circuit includes an interconnect formed within the dielectric material and in electrical contact with the contact structure.

Abstract: Methods for fabricating integrated circuits using chemical mechanical planarization (CMP) for recessing metal are provided. In an embodiment, a method for fabricating an integrated circuit includes filling a trench with a metal and forming an overburden portion of the metal outside of the trench. The method further includes performing a planarization process with an etching slurry to remove the overburden portion of the metal and to recess the metal within the trench.