Abstract: Disclosed are a gate driving circuit and a driving method thereof, and a display device using the driving circuit. In the gate driving circuit, a Qn node in a nth-stage circuit is precharged when a Qn?1 node output signal in a previous-stage driving circuit and a Qn+1 node output signal in a next-stage driving circuit are both at high levels, and thus stability of a Gn output end in the nth-stage circuit can be greatly improved. Meanwhile, a first transistor and a second transistor are connected in series, and a third transistor and a fourth transistor are connected in series.

Abstract: A scanning driving circuit includes a scanning-level-signal-generation module and a scanning-signal-output-module. The scanning-level-signal-generation module is configured to input an (N?1)th stage scanning signal, an (N+1)th stage scanning signal, and a reset signal, generate a scanning level signal based on the (N?1)th stage scanning signal, the (N+1)th stage scanning signal, and the reset signal, and hold the scanning level signal. The scanning-signal-output-module, connected to the scanning-level-signal-generation module, is configured to input a clock signal, and configured to output a scanning signal based in the scanning level signal and the clock signal.

Abstract: Disclosed is a gate driving circuit and a display device, which belongs to the technical field of displaying, and resolves a technical problem that a signal transmitted between cascaded gate driving circuits is easily attenuated in the prior art. The gate driving circuit includes a precharging unit circuit, an output unit circuit, and a compensation charging unit circuit; the output unit circuit includes a first reference point and a first clock signal line; and the precharging unit circuit is configured to input a high level to the first reference point before an output period.

Abstract: Disclosed is a gate driving circuit and a display device, which solve the technical problem that the prior art is easy to cause abnormal output of gate driving signals. The gate driving circuit includes a precharge unit circuit, an output unit circuit, and a holding unit circuit. The output unit circuit includes a first reference point and a clock signal line. The holding unit circuit includes a second reference point and a holding signal line, and a holding capacitor is connected between the second reference point and the holding signal line.

Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; an output circuit for generating a scanning driving signal with two-valued high electrical level and outputting to the current level scanning line to drive a pixel unit.

Abstract: Various embodiments of the present technology generally relate to Global Navigation Satellite Systems (GNSS). More specifically, the embodiments of the present technology relate to a smart antenna module resistant to RFI saturation for dual-frequency GNSS receivers. In some embodiments, a dynamically configured antenna module architecture can be for a dual-band (or multi-frequency) GNSS receiver that can adapt to different RFI conditions by performing corresponding working modes. For example, some embodiments of the smart antenna can measure (e.g., using a power detector) the power of an incoming multi-frequency signal to determine when the multifrequency signal is saturated. Then, using control logic the smart antenna can determine which frequency in the multi-frequency signal is usable and isolate (e.g. using radio frequency components) a frequency that is not saturated. A position estimate can then be generated based on the isolated multi-frequency signal.

Abstract: The present disclosure proposes a GOA circuit having GOA units connected in a serial. Each GOA unit includes a scan-control module, an output module, a pull-down module, and an output adjusting module. By using the output adjusting module formed by a ninth TFT, a tenth TFT, an eleventh TFT, and a twelfth TFT, the voltage level of a fourth node transits between the high voltage level and the low voltage level with the second clock signal in either forward scanning or backward scanning. Compared with the conventional technology where the high and low voltage levels of the output terminal are mainly realized using the second TFT, the GOA circuit realizes that the output ability of the output terminal enhances and the charging capacity of in-plane pixels upgrades in the same period of time to improve the display effect of the liquid crystal panel.

Abstract: Disclosed are a gate driving circuit, a driving method thereof, and a display device which comprises the gate driving circuit. In the gate driving circuit, the Qn node in the nth stage circuit is precharged when an output signal of a Qn?1 node in a previous stage driving circuit and an output signal of a Qn+1 node in a next stage driving circuit are both in a high-level state. Both the Qn?1 node and the Qn+1 node are at low levels when the gate driving circuit is in an All Gate On display state, and thus a possibility of current leakage from the Qn, node can be substantially reduced.

Abstract: The invention generally relates to zero volt mass spectrometry probes and systems. In certain embodiments, the invention provides a system including a mass spectrometry probe including a porous material, and a mass spectrometer (bench-top or miniature mass spectrometer). The system operates without an application of voltage to the probe. In certain embodiments, the probe is oriented such that a distal end faces an inlet of the mass spectrometer. In other embodiments, the distal end of the probe is 5 mm or less from an inlet of the mass spectrometer.

Abstract: Disclosed are a gate driving circuit and a driving method thereof, and a display device using the driving circuit. In the gate driving circuit, a Qn node in a nth-stage circuit is precharged when a Qn?1 node output signal in a previous-stage driving circuit and a Qn+1 node output signal in a next-stage driving circuit are both at high levels, and thus stability of a Gn output end in the nth-stage circuit can be greatly improved. Meanwhile, a first transistor and a second transistor are connected in series, and a third transistor and a fourth transistor are connected in series.

Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a tenth TFT (T10), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T9 and T10 so as to achieve forward and backward scanning without D2U and U2D control signals, which facilitates narrow border design and simplifies corresponding driving timing and reduce IC cost. The pre-charging unit formed by T1, T9, T3, and T10 effectively improves the current leakage and ensures GOA circuit stability.

Abstract: Disclosed is an array substrate and a method for manufacturing the same, a liquid crystal display panel, wherein the array substrate includes: a first material layer and a first conductive layer formed on the first material layer, wherein a region of the first material layer that is not covered by the first conductive layer is etched away in whole or in part along a thickness direction. The array substrate can enable an effective gap of a liquid crystal cell to be increased, thereby improving the transmittance of the panel, and meanwhile can ensure that the response time of the liquid crystal display panel containing the array substrate will not be increased.

Abstract: The present invention provides a method for manufacturing a color filter substrate, the method comprises providing a substrate body with a surface of the substrate body having the pixel unit areas; defining a dividing line on the substrate body; defining a dividing line on the substrate body; marking two sides of the auxiliary area as a predetermined displaying area and a predetermined shielding area, marking first regions in the predetermined displaying area, marking second regions in the predetermined shielding area, and marking third regions in other areas; and forming a shielding layer in each of the second regions and at least one third region.

Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; a leakage prevention circuit to preform a process to the leakage of the input circuit; an output circuit to generate a scanning driving signal and output to the level scanning line to drive a pixel unit.

Abstract: The present disclosure provides a scanning drive circuit and a flat display device, the scanning drive circuit includes a plurality of cascaded scanning driving units, each scanning driving unit includes a forward-reverse scanning circuit used to control the forward scan and the reverse scan; a input circuit used to charge the pull-up and pull-down control signal point; a charge compensating circuit used to compensating charge the pull-up and pull-down control signal point; a output circuit generating the scanning driving signal to the present scanning line driving the pixel unit.

Abstract: The present application discloses a scanning driving circuit and a flat display apparatus, the scanning driving circuit includes a plurality of cascaded scanning driving unit, each scanning driving unit including a forward and reverse scanning circuit for controlling the forward or reverse scanning; an input circuit to perform charging to the pull-up control signal point and the pull-down control signal point; an output circuit for generating a scanning driving signal with two-valued high electrical level and outputting to the current level scanning line to drive a pixel unit.

Abstract: The present invention relates to a GOA circuit. The GOA circuit comprises: a first thin film transistor (T1) to a fourteenth thin film transistor (T14), a first capacitor (C1) and a second capacitor (C2). The present invention adds a control unit consisted of thin film transistors (T9-T14) on the basis of the GOA circuit structure according to prior art, and a set of control signals (Select1, Select2) of which phases are opposite is introduced. The main function is to divide the gate output of the GOA circuit into two. In some special display mode, the frequency corresponded with Data signal will be halved, and the corresponding drive power consumption will be decreased. The present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit for having a certain help to the development of the narrow frame technology.

Abstract: The invention generally relates to zero volt mass spectrometry probes and systems. In certain embodiments, the invention provides a system including a mass spectrometry probe including a porous material, and a mass spectrometer (bench-top or miniature mass spectrometer). The system operates without an application of voltage to the probe. In certain embodiments, the probe is oriented such that a distal end faces an inlet of the mass spectrometer. In other embodiments, the distal end of the probe is 5 mm or less from an inlet of the mass spectrometer.

Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a tenth TFT (T10), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T9 and T10 so as to achieve forward and backward scanning without D2U and U2D control signals, which facilitates narrow border design and simplifies corresponding driving timing and reduce IC cost.

Abstract: The present invention relates to a GOA circuit. The GOA circuit of the present invention comprises a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises: a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), an eighth thin film transistor (T8), a ninth thin film transistor (T9), a tenth thin film transistor (T10), a first capacitor (C1) and a second capacitor (C2). Moreover, two control signals (Select1, Select2) are introduced. The present invention provides a new GOA circuit. The circuit possesses MLG function, which can effectively reduce the feedthrough and improve the Vcom uniformity in the panel to promote the quality of the image display.