Abstract: The present disclosure provides a display panel including a display area and a non-display area, a base substrate, a plurality of thin film transistors, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area, a ground line area and an insulating layer. The thin film transistor includes a gate, a gate insulating layer, a source and a drain. The non-display area includes a first side and a second side; the array substrate row driving circuit respectively forms a first gap and a second gap with the first test signal line area and the second test signal line area, an orthographic projection of the ground line area on the base substrate is in the projection of the second test signal line area in the base substrate. The present disclosure also provides a display device.

Abstract: A GOA electric circuit introduces a resistor and a timing signal, which are used to replace a second capacitor in the existing skills. One terminal of the resistor is connected to a constant high voltage level and the other terminal thereof is connected to a gate electrode of a ninth thin-film transistor. A source electrode of the ninth thin-film transistor is electrically connected to the timing signal. In the stage maintaining the output terminal at low voltage level, the voltage level of the second node can be changed between high and low voltage levels as the timing signal is changed, and the voltage level of the second node is pulled down in a specific frequency. This effectively prevents the second node from being at high voltage level for a long time and avoids the problem of threshold voltage shifting, and therefore improves the stability of GOA electric circuit.

Abstract: A liquid crystal panel and a pixel structure thereof are described. The pixel structure has a common electrode, a protecting layer, a plurality of pixel electrodes, and a plurality of first channels. The protecting layer is located on the common electrode; the pixel electrodes are located on the protecting layer; and the first channels are located between the neighboring pixel electrodes and pass through the protecting layer, so that the first channels expose a top surface of the common electrode.

Abstract: The present invention provides a method for manufacturing a display device includes providing an array substrate with a plurality of pixel unit areas formed on a surface thereof; defining a dividing line; dividing the pixel unit areas to a pixel calculating area, a predetermined displaying area, and a predetermined shielding area, and dividing the pixel calculating area to a first part and a second part by the dividing line; calculating areas of sub pixels according to light extraction efficiencies and effective light extraction areas of the sub pixels; forming a shielding layer according to the areas of the sub pixels.

Abstract: An array substrate for a liquid crystal display panel is disclosed. The array substrate includes a first substrate, a Lower Temperature Polycrystal Silicon (LTPS) Thin-Film-Transistor (TFT) disposed on the first substrate, a color photoresist layer disposed on the LTPS TFT, and multiple photo spacers disposed above the color photoresist layer. A liquid crystal display panel including the array substrate and a second substrate disposed oppositely to the array substrate is also disclosed. The present invention utilizes the second substrate to be aligned with the LTPS TFT array substrate in order to form the liquid crystal display panel. Because the second substrate is a bare substrate (without a pattern), when the second substrate is aligned with the array substrate, the alignment precision is not under consideration. Accordingly, apertures ratios of the liquid crystal display panel do not have difference.

Abstract: Disclosed is a gate driving circuit and a display device, which solve the technical problem that the prior art is easy to cause abnormal output of gate driving signals. The gate driving circuit includes a precharge unit circuit, an output unit circuit, and a holding unit circuit. The output unit circuit includes a first reference point and a clock signal line.

Abstract: A scanning driving circuit includes a scanning-level-signal-generation module and a scanning-signal-output-module. The scanning-level-signal-generation module is configured to input an (N?1)th stage scanning signal, an (N+1)th stage scanning signal, and a reset signal, generate a scanning level signal based on the (N?1)th stage scanning signal, the (N+1)th stage scanning signal, and the reset signal, and hold the scanning level signal. The scanning-signal-output-module, connected to the scanning-level-signal-generation module, is configured to input a clock signal, and configured to output a scanning signal based in the scanning level signal and the clock signal.

Abstract: The present disclosure proposes a GOA circuit based on LTPS TFTs. A ninth TFT is introduced to adjust the high and low voltage levels imposed on the second node P(n). The ninth TFT includes a gate and a source both electrically connected to the second node P(n) and a drain electrically connected to a second clock signal. Such designs make it possible that the level of the second node P(n) is pulled down according to a certain frequency when an output terminal G(n) keeps the low voltage level. So the second node P(n) does not need to keep the high voltage level all the time in the present invention. Also, the fourth and the seventh transistors T4 and T7 do not have the problem of a threshold voltage shift due to a long working time.

Abstract: The invention provides an ESD detection method for array substrate. By connecting the first metal layer on array substrate through the first wire to the first test point, connecting the second metal layer on array substrate through the second wire to the second test point, when ESD occurs on array substrate, the resistance detection device is used to measure the resistance between the first and second test points. If the resistance is positive infinity, ESD did not occur between the first and second metal layers; if the resistance is within a measurable range, ESD occurs between the first and second metal layers. The resistance is used to locate the location of ESD occurrence on array substrate. Compared to known method using microscope to search ESD location, the invention can locate ESD location on array substrate more accurately and rapidly to save time and labor as well as detection cost.

Abstract: The present invention provides an array substrate, a method of manufacturing the same and an In Cell touch control display panel.

Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T8 and T9 connected in parallel between node H and node Qn for conduction. The gate of T8 is connected to Qn?1 (the output signal of the previous GOA unit), and the gate of T9 is connected to Qn+1 (the output signal of the next GOA unit). The invention can provide the function of the known GOA circuit to prevent the stress on TFT T7, can also prevent the output Gn from instability.

Abstract: A GOA substrate includes N shift register units. The first stage shift register unit outputs a scan signal pulse based on a first clock signal and a start signal. The last stage shift register unit outputs a scan signal pulse based on Mth clock signal and the start signal. The start signal has a pulse width starting from a falling edge of the Mth clock signal of the last stage shift register unit when scanning a first frame, and ending at a rising edge of the first clock signal of the first stage shift register unit when scanning a second frame. Since the first and last shift register units are used to drive a scan signal pulse based on the start signal, the present invention reduces the number of wires needed to transmit start signals and simplifies the complexity of the layout design.

Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7),an eighth TFT (T8), a ninth TFT (T9), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T8 and T9 connected in parallel between node H and node Qn for conduction. The gate of T8 is connected to Qn?1 (the output signal of the previous GOA unit), and the gate of T9 is connected to Qn+1 (the output signal of the next GOA unit). The invention can provide the function of the known GOA circuit to prevent the stress on TFT T7, can also prevent the output Gn from instability.

Abstract: The invention provides a GOA circuit, the forward-and-reverse scan control module of the GOA circuit comprising: a first TFT and a third TFT, the first TFT having the gate connected to the gate scan drive signal of the (n?1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to a first node; and the third TFT having the gate connected to the gate scan drive signal of the (n+1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to the first node. With the two TFTs to control the switching of forward and reverse scanning of the GOA circuit, the present invention eliminates two control signals without increasing the numbers of TFTs and capacitors. As such, the selection for IC is increased, which enables the realization of narrow border LCD.

Abstract: The invention provides a GOA circuit, using the ninth and tenth TFTs and the resistor to control the voltage level of the third node, wherein ninth TFT having the gate connected to the m-th clock signal, the source connected to the first constant voltage, and the drain connected to one end of the resistor; the tenth TFT having the gate connected to the (m+2)-th clock signal, the source connected to the second constant voltage, and the drain connected to the other end of the resistor. Through the m-th and the (m+2)-th clock signal to control the ninth and the tenth TFTs to become conductive alternately, the present invention can charge and discharge the third node regularly to prevent the threshold voltage shift of the key TFT because the third node stays high for extended time, and ensure the stability of GOA circuit.

Abstract: A gate driving circuit disposed on an array substrate and an LCD using the same are described. The gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units. The gate driving circuit unit comprises an input module, a reset module, a latch module and a signal processing module. The signal processing module receives the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal. The present invention utilizes less clock signals and transistors, which is favorable to the narrower LCD's frame design and solves the problem of manufacturing process restriction of the LCD panel.

Abstract: The present invention relates to a GOA circuit. The GOA circuit comprises: a first thin film transistor (T1) to a fourteenth thin film transistor (T14), a first capacitor (C1) and a second capacitor (C2). The present invention adds a control unit consisted of thin film transistors (T9-T14) on the basis of the GOA circuit structure according to prior art, and a set of control signals (Select1, Select2) of which phases are opposite is introduced. The main function is to divide the gate output of the GOA circuit into two. In some special display mode, the frequency corresponded with Data signal will be halved, and the corresponding drive power consumption will be decreased. The present invention provides a GOA circuit, which can effectively reduce the layout space occupied by the GOA circuit for having a certain help to the development of the narrow frame technology.

Abstract: The invention provides a GOA circuit, comprising a plurality of GOA units, for a positive integer n, n-th GOA unit comprising: a first TFT (T1), a second TFT (T2), a third TFT (T3), a fourth TFT T(4), a fifth TFT (T5), a sixth TFT (T6), a seventh TFT (T7), an eighth TFT (T8), a ninth TFT (T9), a tenth TFT (T10), a first capacitor (C1) and a second capacitor (T2). The invention, based on known GOA circuit, uses T9 and T10 so as to achieve forward and backward scanning without D2U and U2D control signals, which facilitates narrow border design and simplifies corresponding driving timing and reduce IC cost. The pre-charging unit formed by T1, T9, T3, and T10 effectively improves the current leakage and ensures GOA circuit stability.

Abstract: The present invention relates to a GOA circuit. The GOA circuit of the present invention comprises a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises: a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), an eighth thin film transistor (T8), a ninth thin film transistor (T9), a tenth thin film transistor (T10), a first capacitor (C1) and a second capacitor (C2). Moreover, two control signals (Select1, Select2) are introduced. The present invention provides a new GOA circuit. The circuit possesses MLG function, which can effectively reduce the feedthrough and improve the Vcom uniformity in the panel to promote the quality of the image display.

Abstract: Provided is an LTPS array substrate and a liquid crystal display panel, wherein the LTPS array substrate comprises: a first common electrode layer; a passivation layer, which is formed on the first common electrode layer, and has a first via hole formed therein; a pixel electrode layer, which is formed on the passivation layer; and a second common electrode layer, which is formed on the passivation layer, located between pixel electrodes corresponding to two adjacent sub-pixels in the pixel electrode layer, electrically isolated from the pixel electrode layer, and electrically connected to the first common electrode layer through the first via hole. The array substrate is capable of significantly enhancing the intensity of an electric field at an edge region of the adjacent sub-pixels, thereby increasing the transmittance at this region.