Patents by Inventor Yakub Aliyu
Yakub Aliyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120279865Abstract: Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections.Type: ApplicationFiled: November 4, 2011Publication date: November 8, 2012Applicant: Sonavation, Inc.Inventors: Louis Regniere, Yakub Aliyu, Rainer M. Schmitt, Theodore M. Johnson, Ronald A. Kropp, Christian Liautaud, Deda Diatezua, Isaac R. Abothu, De Liufu, Richard Irving, Patrick D. Brown, Walter C. Mick, William H. Tanubrata, Omid S. Jahromi, John Boudreaux, David B. Clarke, Jack S. Chorpenning, Bryce M. Barbato, Honorio R. Ulep, William R. Robinson, JR.
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Publication number: 20110269307Abstract: Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections.Type: ApplicationFiled: May 2, 2011Publication date: November 3, 2011Applicant: Sonavation, Inc.Inventors: Yakub Aliyu, Deda Diatezua
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Patent number: 7452808Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: GrantFiled: November 15, 2004Date of Patent: November 18, 2008Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
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Patent number: 7060613Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: GrantFiled: November 15, 2004Date of Patent: June 13, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Xu Yi
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Patent number: 6987321Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: GrantFiled: November 21, 2003Date of Patent: January 17, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6967162Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: GrantFiled: November 15, 2004Date of Patent: November 22, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
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Publication number: 20050112799Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: November 15, 2004Publication date: May 26, 2005Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu
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Publication number: 20050090102Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: November 15, 2004Publication date: April 28, 2005Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
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Publication number: 20050090037Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: October 29, 2004Publication date: April 28, 2005Inventors: Yakub Aliyu, Simon Chooi, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy
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Publication number: 20050090039Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: November 15, 2004Publication date: April 28, 2005Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
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Patent number: 6821888Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: GrantFiled: February 13, 2002Date of Patent: November 23, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Publication number: 20040227247Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: ApplicationFiled: November 21, 2003Publication date: November 18, 2004Applicant: CHARTERED SEMICONDUCTOR MANFACTURING LTD.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subbash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6813796Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: GrantFiled: February 3, 2003Date of Patent: November 9, 2004Assignee: Chartered SemiconductorInventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6803305Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.Type: GrantFiled: April 10, 2002Date of Patent: October 12, 2004Assignee: Chartered Semiconductor Manufacturing LimitedInventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Ding Yi
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Publication number: 20040077174Abstract: A method for forming a high aspect ratio via. In one embodiment, the present method comprises providing a first material into which a high aspect ratio via is to be formed. The present embodiment then deposits a first layer of a second material above the first material. Next, the present method recites forming an opening in the first layer of the second material. A second layer of the second material is then deposited above the first layer of the second material and into the opening formed into the first layer of the second material. The present embodiment then etches the second layer of the second material such that the opening extends through the second layer of the second material and through the first layer of the second material. In so doing, the opening is configured to have a profile conducive to the adherence of overlying material thereto.Type: ApplicationFiled: October 18, 2002Publication date: April 22, 2004Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING LTD., AGILENT TECHNOLOGIES, INC.Inventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu
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Patent number: 6720204Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.Type: GrantFiled: April 11, 2002Date of Patent: April 13, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6705512Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.Type: GrantFiled: March 15, 2002Date of Patent: March 16, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Patent number: 6692579Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.Type: GrantFiled: January 19, 2001Date of Patent: February 17, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
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Patent number: 6686279Abstract: A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target.Type: GrantFiled: April 1, 2002Date of Patent: February 3, 2004Assignee: Chartered Semiconductor Manufacturing LimitedInventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Lee Yuan Ping
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Patent number: 6683002Abstract: Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.Type: GrantFiled: August 10, 2000Date of Patent: January 27, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu