Patents by Inventor Yakub Aliyu
Yakub Aliyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030194856Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.Type: ApplicationFiled: April 10, 2002Publication date: October 16, 2003Inventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Ding Yi
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Publication number: 20030192943Abstract: A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.Type: ApplicationFiled: April 11, 2002Publication date: October 16, 2003Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: John Leonard Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Publication number: 20030186542Abstract: A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target.Type: ApplicationFiled: April 1, 2002Publication date: October 2, 2003Inventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Lee Yuan Ping
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Publication number: 20030140943Abstract: A new apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: ApplicationFiled: February 3, 2003Publication date: July 31, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Patent number: 6540841Abstract: A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface.Type: GrantFiled: June 30, 2000Date of Patent: April 1, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Sudipto Ranendra Roy, Subhash Gupta, Simon Chooi, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho
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Publication number: 20030032275Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.Type: ApplicationFiled: February 13, 2002Publication date: February 13, 2003Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Patent number: 6475810Abstract: A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.Type: GrantFiled: August 10, 2000Date of Patent: November 5, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu, Simon Chooi, Yakub Aliyu
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Patent number: 6429117Abstract: A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.Type: GrantFiled: July 19, 2000Date of Patent: August 6, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: John Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Publication number: 20020100794Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.Type: ApplicationFiled: March 15, 2002Publication date: August 1, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Publication number: 20020096190Abstract: A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity.Type: ApplicationFiled: January 19, 2001Publication date: July 25, 2002Applicant: Chartered Semiconductor Manufacturing Inc.Inventors: Sudipto Ranendra Roy, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Paul Kwok Keung Ho, Subhash Gupta
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Patent number: 6417088Abstract: A method of forming a conductive cap layer over a metal bonding pad comprises the following steps. A semiconductor structure is provided having an exposed, recessed metal bonding pad within a layer opening. The layer has an upper surface. The exposed metal bonding pad is treated with a solution containing soluble metal ions to form a conductive cap over the metal bonding pad. The conductive cap layer is comprised of the solution metal and has a predetermined thickness. An external bonding element may then be bonded to the conductive cap, forming an electrical connection with the metal bonding pad.Type: GrantFiled: July 24, 2000Date of Patent: July 9, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kwok Keung Paul Ho, Yi Xu, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Patent number: 6415973Abstract: A method of bonding a bonding element to a metal bonding pad, comprising the following steps. A semiconductor structure having an exposed metal bonding pad within a passivation layer opening is provided. The bonding pad has an upper surface. A bonding element is positioned to contact the bonding pad upper surface. A bonding solution is applied within the passivation layer opening, covering the bonding pad and a portion of the bonding element. The structure is annealed by heating said bonding element to selectively solidify the bonding solution proximate said contact of said bonding element to said bonding pad, bonding the bonding element to the bonding pad.Type: GrantFiled: July 18, 2000Date of Patent: July 9, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Mei Sheng Zhou, Yakub Aliyu, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Patent number: 6391783Abstract: A method of forming a metal plug, comprising the following steps. An etched dielectric layer, over a conductive layer, over a semiconductor structure are provided. The etched dielectric layer having a via hole and an exposed periphery. The etched dielectric layer is treated with at least one alkaline earth element source to form an in-situ metal barrier layer within the dielectric layer exposed periphery. A metal plug is formed within the via hole wherein the in-situ metal barrier layer prevents diffusion of the metal from the metal plug into the dielectric oxide layer.Type: GrantFiled: July 13, 2000Date of Patent: May 21, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: John Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
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Patent number: 6378759Abstract: A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.Type: GrantFiled: July 18, 2000Date of Patent: April 30, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kwok Keung Paul Ho, Simon Chooi, Yi Xu, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy
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Publication number: 20020048950Abstract: An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.Type: ApplicationFiled: June 18, 2001Publication date: April 25, 2002Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Yakub Aliyu, Simon Chooi, Mei Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Yi Xu
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Patent number: 6365508Abstract: A new method to avoid post-etch cleaning in a metallization process is described. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts is as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.Type: GrantFiled: July 18, 2000Date of Patent: April 2, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Xu Yi, Simon Chooi, Yakub Aliyu
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Patent number: 6358821Abstract: A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.Type: GrantFiled: July 19, 2000Date of Patent: March 19, 2002Assignee: Chartered Semiconductor Manufacturing Inc.Inventors: Subhash Gupta, Simon Chooi, Sudipto Ranendra Roy, Paul Kwok Keung Ho, Xu Yi, Yakub Aliyu, Mei Sheng Zhou, John Leonard Sudijono
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Patent number: 6350689Abstract: A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.Type: GrantFiled: April 23, 2001Date of Patent: February 26, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Paul Ho, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Yi Xu
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Patent number: 6340608Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.Type: GrantFiled: July 7, 2000Date of Patent: January 22, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Xu Yi
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Method for minimizing copper diffusion by doping an inorganic dielectric layer with a reducing agent
Patent number: 6309982Abstract: A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.Type: GrantFiled: March 12, 2001Date of Patent: October 30, 2001Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Simon Chooi, Yi Xu, Yakub Aliyu, Mei-Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho