Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

Abstract: A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.

Abstract: A semiconductor package includes a semiconductor chip disposed over a first main surface of a first substrate, a package lid disposed over the semiconductor chip, and spacers extending from the package lid through corresponding holes in the first substrate. The spacers enter the holes at a first main surface of the first substrate and extend beyond an opposing second main surface of the first substrate.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a substrate including an electrical component; forming a capacitor structure in the substrate, proximal to a heterogeneous interface of the substrate, and physically and electrically isolated from the electrical component; forming a conductive terminal over and electrically connected with the capacitor structure; and contacting the conductive terminal with a probe to measure an electrical parameter of the capacitor structure, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.

Abstract: A semiconductor package structure includes an interconnection structure having a first surface and a second surface opposite to the first surface, a die surrounded by a molding compound over the first surface of the interconnection structure, and a passive device surrounded by a dielectric structure over the second surface of the interconnection structure. The passive device is electrically coupled to the die by the interconnection structure.

Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.

Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.

Abstract: A semiconductor package structure includes an interconnection structure having a first surface and a second surface opposite to the first surface, a die surrounded by a molding compound over the first surface of the interconnection structure, and a passive device surrounded by a dielectric structure over the second surface of the interconnection structure. The passive device is electrically coupled to the die by the interconnection structure.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a substrate including an electrical component; forming a capacitor structure in the substrate, proximal to a heterogeneous interface of the substrate, and physically and electrically isolated from the electrical component; forming a conductive terminal over and electrically connected with the capacitor structure; and contacting the conductive terminal with a probe to measure an electrical parameter of the capacitor structure, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.

Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.

Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.