Patents by Inventor Yang-Che CHEN

Yang-Che CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10629673
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a conductive terminal exposed from a passivation; forming a capacitor structure under the passivation proximal to a heterogeneous interface; electrically connecting the capacitor structure to the conductive terminal and isolating the capacitor structure from other electrical components in the semiconductor structure; and probing the conductive terminal to measure an electrical parameter of the capacitor structure covered by the passivation, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Publication number: 20200118984
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Publication number: 20200098851
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a conductive terminal exposed from a passivation; forming a capacitor structure under the passivation proximal to a heterogeneous interface; electrically connecting the capacitor structure to the conductive terminal and isolating the capacitor structure from other electrical components in the semiconductor structure; and probing the conductive terminal to measure an electrical parameter of the capacitor structure covered by the passivation, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 18, 2019
    Publication date: March 26, 2020
    Inventors: YANG-CHE CHEN, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • Publication number: 20200075435
    Abstract: A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.
    Type: Application
    Filed: January 22, 2019
    Publication date: March 5, 2020
    Inventors: YANG-CHE CHEN, WEI-YU CHOU, HONG-SENG SHUE, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • Patent number: 10510734
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Publication number: 20190333829
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che CHEN, Tsung-Te CHOU, Chen-Hua LIN, Huang-Wen TSENG, Chwen-Ming LIU
  • Patent number: 10347548
    Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 9, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 10276548
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Publication number: 20190115326
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 18, 2019
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Publication number: 20180156865
    Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 7, 2018
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Publication number: 20180076184
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Application
    Filed: August 4, 2017
    Publication date: March 15, 2018
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Patent number: 9254999
    Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a substrate and a MEMS sensor over the substrate. The MEMS sensor includes a floating heater disposed over the substrate. The MEMS sensor further includes a heat sink disposed over the substrate and at a side of the floating heater, and the heat sink has an air gap with the floating heater. The MEMS sensor further includes a first plurality of vias formed through the heat sink and thermally connected to the first substrate.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: February 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Bruce C. S. Chou, Yang-Che Chen, Chen-Chih Fan
  • Publication number: 20150137303
    Abstract: Embodiments of mechanisms for forming a micro-electro mechanical system (MEMS) device are provided. The MEMS device includes a substrate and a MEMS sensor over the substrate. The MEMS sensor includes a floating heater disposed over the substrate. The MEMS sensor further includes a heat sink disposed over the substrate and at a side of the floating heater, and the heat sink has an air gap with the floating heater. The MEMS sensor further includes a first plurality of vias formed through the heat sink and thermally connected to the first substrate.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Bruce C.S. CHOU, Yang-Che CHEN, Chen-Chih FAN