Abstract: Exemplary embodiments of the present disclosure relate to methods of manufacturing display panels and display panels. The method of manufacturing a display panel includes: preparing a driving film layer on a substrate of the display panel, and removing at least a removal part of the driving film layer along a slotting-cutting path of the display panel; performing a cutting process on a slotted area of the display panel along the slotting-cutting path. By removing at least a removal part of the driving film layer along the slotting-cutting path before performing the cutting process on the slotted area of the display panel, problems such as thermal damage to the driving film layer and the like can be prevented, so that the problem of reducing the strength of the screen body in the slotted area can be avoided, and the quality of the product can be improved.

Abstract: The present disclosure relates to a display screen and a display device. The display screen includes a display area, and the display area includes a pixel area and a non-pixel area located around the pixel area. The display screen includes a plurality of film layers stacked in sequence. The plurality of film layers are provided with at least one support pillar therein. The support pillar is located in the non-pixel area and is embedded in at least two film layers along a longitudinal direction orthogonal to a surface of the display screen. In addition, a display device including the aforementioned display screen is provided.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: Provided are a method and a device for detecting a genetic mutation, and a kit for typing genotypes of a pregnant woman and a fetus. The method comprises: performing high-throughput sequencing on free DNA in a pregnant woman's peripheral blood to obtain sequencing data; comparing the sequencing data with reference genome to obtain SNP sites; performing mixed genotyping on each SNP site to obtain target genotypes for each SNP site; and selecting a mutation site that causes the gene mutation from the genotype of the fetus in the target genotypes.

Abstract: An aqueous solvent composition is provided, comprising a nucleophilic component having one or more sterically unhindered primary or secondary amine moieties, a Brønsted base component having one or more basic nitrogen moieties, a water-soluble organic solvent, and water. A biphasic composition is provided, comprising one or more carbamate compounds, one or more conjugate acids of Brønsted base, a water-soluble organic solvent, and water. A biphasic CO2 absorption process is also provided, utilizing the biphasic solvent composition.

Abstract: Exemplary embodiments of the present disclosure relate to methods of manufacturing display panels and display panels. The method of manufacturing a display panel includes: preparing a driving film layer on a substrate of the display panel, and removing at least a removal part of the driving film layer along a slotting-cutting path of the display panel; performing a cutting process on a slotted area of the display panel along the slotting-cutting path. By removing at least a removal part of the driving film layer along the slotting-cutting path before performing the cutting process on the slotted area of the display panel, problems such as thermal damage to the driving film layer and the like can be prevented, so that the problem of reducing the strength of the screen body in the slotted area can be avoided, and the quality of the product can be improved.

Abstract: The present invention discloses a distributed device for simultaneously measuring strain and temperature based on optical frequency domain reflection, comprising a tunable laser, a 1:99 beam splitter, a main interferometer system, a light source phase monitoring system based on an auxiliary interferometer, an acquisition device and a computer processing unit, wherein the main interferometer system comprises two Mach-Zehnder interferometers, and two optical fibers having different cladding diameters are arranged in parallel as sensing fibers. Due to the difference in temperature and strain coefficients of optical fibers of the same diameter, the temperature and strain values during changing the temperature and strain simultaneously can be obtained by matrix operation, thereby achieving an effect of eliminating cross sensitivity of temperature and strain sensing in optical frequency domain reflection.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: A touch control apparatus for a virtual reality device and a virtual reality system. The touch control apparatus comprises a touch control panel, the touch control panel comprises a key area and a touch area, the touch area employs a touchpad of a multi-touch type. The key area is provided with a plurality of function keys, and the touch area is provided with a plurality of reference point keys. The reference point keys are for controlling size and position of a manipulating area in a displaying visual field of an external virtual reality device.

Abstract: Disclosed is a system for measuring temperature in an integrated circuit (IC) device. The system includes a diode-based temperature sensor comprising a first plurality of diodes coupled between a power supply pin of the IC device and a ground pin of the IC device and a second plurality of diodes coupled between the power supply pin and the ground pin, and a voltage sensing circuit configured to detect a voltage difference between the first plurality of diodes and the second plurality of diodes.

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

Abstract: The present invention discloses a distributed device for simultaneously measuring strain and temperature based on optical frequency domain reflection, comprising a tunable laser, a 1:99 beam splitter, a main interferometer system, a light source phase monitoring system based on an auxiliary interferometer, an acquisition device and a computer processing unit, wherein the main interferometer system comprises two Mach-Zehnder interferometers, and two optical fibers having different cladding diameters are arranged in parallel as sensing fibers. Due to the difference in temperature and strain coefficients of optical fibers of the same diameter, the temperature and strain values during changing the temperature and strain simultaneously can be obtained by matrix operation, thereby achieving an effect of eliminating cross sensitivity of temperature and strain sensing in optical frequency domain reflection.

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC.

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

Abstract: Dynamically controlling voltage provided to three-dimensional (3D) integrated circuits (ICs) (3DICs) to account for process variations measured across interconnected IC tiers of 3DICs are disclosed herein. In one aspect, a 3DIC process variation measurement circuit (PVMC) is provided to measure process variation. The 3DIC PVMC includes stacked logic PVMCs configured to measure process variations of devices across multiple IC tiers and process variations of vias that interconnect multiple IC tiers. The 3DIC PVMC may include IC tier logic PVMCs configured to measure process variations of devices on corresponding IC tiers. These measured process variations can be used to dynamically control supply voltage provided to the 3DIC such that operation of the 3DIC approaches a desired process corner. Adjusting supply voltage using the 3DIC PVMC takes into account interconnected properties of the 3DIC such that the supply voltage is adjusted to cause the 3DIC to operate in the desired process corner.