Abstract: Laser annealing methods for integrated circuits (IC) are disclosed. In particular, an upper surface of an integrated circuit is annealed with a laser using a brief burst of light from the laser. In an exemplary embodiment, the brief burst of light from the laser lasts approximately fifty (50) to five hundred (500) microseconds. This brief burst will raise the temperature of the surface to approximately 1200° C.

Abstract: Methods of designing three dimensional integrated circuits (3DIC) and related systems and components are disclosed. An exemplary embodiment provides an improved cell library for use with existing place and route software in such a manner that the modified software allows building 3DICs. The improved cell library includes 3D cells that have the footprint of the cell projected onto a two dimensional (2D) image. The projected view may then be discounted to the portion of the cell that is within an upper tier so that the cell appears to the place and route software to be a 2D cell. The discounted 2D image is then used by the place and route software. Such cells allow a circuit designer to leverage the existing 2D place and route tools as well as static timing analysis tools.

Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

Abstract: Embodiments disclosed in the detailed description include digital temperature estimators (DTEs) disposed in integrated circuits (ICs) for estimating temperature within the ICs. Related systems and methods are also disclosed. In one embodiment, the DTEs can be used to estimate temperatures in an IC by implementing a temperature estimation model (TEM). The TEM can provide an estimated temperature of an IC block disposed in the IC based on activity event(s) associated with the IC block, as opposed to providing temperature sensors in the IC to measure temperature of the IC block directly. The DTEs can be operated in real time so that power and/or thermal regulation systems of the IC can obtain accurate and reliable temperature estimation from the DTEs. In this manner, thermal dissipation in the IC may be regulated more effectively.

Abstract: A combination television monitor stand and wall mount is presented. The combination stand and mount has an assembly of parts that can be assembled into two different configurations. The parts assembly includes a base plate, brackets, screws, and a stand cover. In a stand configuration, the described apparatus functions as a table stand for a television or computer monitor. In a wall mount configuration, the described apparatus allows a monitor to be mounted to a wall. A second embodiment provides a stand configuration having a neck pivotably attached to a base plate by a hinge, and a locking lever arm supporting the neck when the neck is in an upright position.

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract: Compositions and methods related to the removal of acidic gas. In particular, the present disclosure relates to a composition and method for the removal of acidic gas from a gas mixture using a solvent comprising a blend of piperazine and at least one diamine or triamine.

Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

Abstract: Embodiments disclosed in the detailed description include a complete system-on-chip (SOC) solution using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) integration technology. The present disclosure includes example of the ability to customize layers within a monolithic 3DIC and the accompanying short interconnections possible between tiers through monolithic intertier vias (MIV) to create a system on a chip. In particular, different tiers of the 3DIC are constructed to support different functionality and comply with differing design criteria. Thus, the 3DIC can have an analog layer, layers with higher voltage threshold, layers with lower leakage current, layers of different material to implement components that need different base materials and the like. Unlike the stacked dies, the upper layers may be the same size as the lower layers because no external wiring connections are required.

Abstract: A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

Abstract: A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided.

Abstract: A three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract: Ion-reduced, ion cut-formed three-dimensional (3D) integrated circuits (IC) (3DICs) are disclosed. Related methods and systems are also disclosed. During an ion-cut process for forming a monolithic 3DIC, extra ions are implanted in the donor wafer to effectuate the ion-cut. Excess, residual implanted ions remain implanted in a top layer of the transfer layer of the 3DIC. However, these residual implanted ions can interfere with operation of electronic components in the 3DIC. In this regard, the 3DIC and methods disclosed herein involve reduction or removal of the residual extra ions before further electronic components are created and layered in a 3DIC. In this manner, the extra charge elements introduced by such extra ions are reduced or removed providing for better functionality in the completed device.

Abstract: A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A graphene layer is a sheet like layer made of pure carbon, at least one atom thick with atoms arranged in a regular hexagonal pattern. A graphene layer may be disposed between any number of adjacent tiers in the 3DIC. In exemplary embodiments, the graphene layer provides an electromagnetic interference shield between adjacent tiers or layers in the 3DIC to reduce crosstalk between the tiers. In other exemplary embodiments, the graphene layer(s) can be disposed in the 3DIC to provide a heat sink that directs and dissipates heat to peripheral areas of the 3DIC. In some embodiments, the graphene layer(s) are configured to provide both EMI shielding and heat shielding.

Abstract: A semiconductor device and methods of making a semiconductor device using graphene are described. A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.

Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

Abstract: The disclosed embodiments comprise a multi-stage circuit operating across different power domains. The multi-stage circuit may be implemented as a master-slave flip-flop circuit integrated with a level shifter that transfers data across different power domains. The master and slave stages of the flip-flop may be split across two tiers of a 3D IC and may include (i) a level shifter across different power domain integrated within the flip-flop circuit, (ii) reduced one-state writing delays by a self-induced power collapsing technique, (iii) splitting flip-flop power supplies in different tiers using monolithic 3D IC technology, and (iv) cross power domain data transfer between 3D IC tiers.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.