Abstract: The tether of the present invention can prevent an appliance, such as a television or monitor, from toppling off furniture, such as a dresser, upon which the appliance rests. The tether attaches to the appliance and to the wall using surface-mounts. Embodiments of the tether may include some or all of the following features: (1) a length-adjuster to facilitate a snug fit; (2) loops and elastic components to maintain tautness while permitting tilt and swivel of the electronic device; (3) quick-release(s) to allow the electronic device to be moved without having to detach the surface-mounts from the wall or from the electronic device; (4) an adhesive surface for easy installation. Methods for using the tether are described.

Abstract: Spin transistors and related memory, memory systems, and methods are disclosed. A spin transistor is provided by at least two magnetic tunnel junctions (MTJs) with a shared multiferroic layer. The multiferroic layer is formed from a piezoelectric (PE) thin film over a ferromagnetic thin film (FM channel) with a metal electrode (metal). The ferromagnetic layer functions as the spin channel and the piezoelectric layer is used for transferring piezoelectric stress to control the spin state of the channel. The MTJ on one side of the shared layer forms a source and the MTJ on the other side is a drain for the spin transistor.

Abstract: High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

Abstract: Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated.

Abstract: A current lead for the superconducting magnet of a magnetic resonance system, the superconducting magnet being refrigerated by a cold head, has a positive current lead and a negative current lead electrically connected to the superconducting magnet for magnetization thereof. The cold head is electrically connected to the superconducting magnet and is used as one of the positive and negative current leads. The cold head is used as the positive current lead or the negative current lead so as to reduce the number of current leads as well as the heat conducted by the current lead, therefore it maintains a stable superconducting environment more efficiently. Furthermore, the cold head and the current lead can be provided in the same conduit without the need to design a separated turret tube and side tube, and the structure of the current leads of the superconducting magnet of the magnetic resonance system is simplified.

Abstract: A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively.

Abstract: The present invention provides a medical image information management system and a program product which allow generating a list containing the information on the medical images such as a work list, with a better workability. The medical image information management system for managing the information on the medical images includes a search device for searching the information regarding medical image using a desired query, a query storing device for storing the query established by the user, and a list generating device for generating a list containing the information on the medical images extracted as the result of search based on the query established by the user and storing in a folder.

Abstract: Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A current lead for the superconducting magnet of a magnetic resonance system, the superconducting magnet being refrigerated by a cold head, has a positive current lead and a negative current lead electrically connected to the superconducting magnet for magnetization thereof. The cold head is electrically connected to the superconducting magnet and is used as one of the positive and negative current leads. The cold head is used as the positive current lead or the negative current lead so as to reduce the number of current leads as well as the heat conducted by the current lead, therefore it maintains a stable superconducting environment more efficiently. Furthermore, the cold head and the current lead can be provided in the same conduit without the need to design a separated turret tube and side tube, and the structure of the current leads of the superconducting magnet of the magnetic resonance system is simplified.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A semiconductor device (151) is provided which comprises (a) a semiconductor substrate (103); (b) a fin (109) comprising a semiconductor material and being in electrical contact with the substrate; (c) a first floating gate (121) disposed on a first side of said fin; and (d) a control gate (107).

Abstract: A method of forming a semiconductor device is provided in which a substrate (102) is provided which has a gate dielectric layer (106) disposed thereon, and a gate electrode (116) having first and second sidewalls is formed over the gate dielectric layer. First (146) and second (150) extension spacer structures are formed adjacent the first and second sidewalls, respectively.

Abstract: A double gated device is made by forming a first gate on top of a first substrate and over a channel. Etching into the substrate, using the gate as a mask, forms recesses that are filled with a material that etches selectively to the material of the substrate that is adjacent to the recesses and under the channel. A second substrate is attached over the first gate so that the major portion of the first substrate can be removed. The portion of the remaining substrate between the source/drain regions is removed to form a gate recess for a second gate. The channel is preferably of a different material from that being etched so that it will act as an etch stop during this step. A sidewall spacer is formed along the sidewall of the gate recess and a second gate is formed in the gate recess to obtain self-aligned gates.

Abstract: A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together.

Abstract: A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure (2106) with alternating source/drain terminals (2120, 2122, 2124, 2126) in which the sources are connected together and the drains are connected together. Gates (2116, 2110) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier (2000) may also be used as a mixer and further as a phase detector.

Abstract: A method for forming a silicon-on-insulator transistor (80) includes forming an active region (82) overlying an insulating layer (122), wherein a portion of the active region provides an intrinsic body region (126). A body tie access region (128) is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode (134) is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion (137) of the body tie access region. The gate electrode is formed having a substantially constant gate length (88) along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes (98,100) are formed adjacent opposite sides of the intrinsic body region.