Abstract: A synapse device, a manufacturing method thereof, and a neuromorphic device including the synapse device are disclosed. The synapse device may include a channel member, a tunnel insulating layer disposed on the channel member, a charge trap layer disposed on the tunnel insulating layer, a blocking insulating layer disposed on the charge trap layer, a gate electrode disposed on the blocking insulating layer, a first terminal and a second terminal respectively connected to first and second regions of the channel member, and first and second conductors respectively bonded to the first and second terminals The charge trap layer may have a multilayer structure including a first trap layer disposed adjacent to the channel member and a second trap layer disposed adjacent to the gate electrode. The first trap layer may have a trap of a shallower level than that of the second trap layer.

Abstract: A ternary logic element including a transistor and a switching element. The transistor includes a channel layer including silicon, an input electrode, an output electrode, and a control electrode. The switching element includes an emitter, a base extending from the emitter, and a collector extending from the base. When a first control voltage is applied to the control electrode, the ternary logic element outputs a first voltage, and when a second control voltage different from the first control voltage is applied to the control electrode, the ternary logic element outputs a second voltage different from the first voltage, and when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, the ternary logic element outputs a third voltage different from the first voltage and the second voltage.

Abstract: Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.

Abstract: A transistor for implementing a photo-responsive neuronal device is disclosed. According to one example embodiment, the transistor includes a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body extended in a horizontal direction on the hole barrier region or the electron barrier region; a source region and a drain region formed at both ends of the floating body; a gate insulating film formed on the floating body; and a gate region formed on the gate insulating film.

Abstract: A steep-slope field-effect transistor and a fabrication method thereof are disclosed. The steep-slope field-effect transistor according to an embodiment of the inventive concept includes a source, a channel region, and a drain formed on a substrate; a gate insulating film formed on an upper portion of the channel region; a floating gate formed on an upper portion of the gate insulating film; a transition layer formed on an upper portion of the floating gate; and a control gate formed on an upper portion of the transition layer. The steep-slope field-effect transistor applies a reference potential or more to the control gate to discharge or bring in at least one charge stored in the floating gate.

Abstract: A synaptic device, a neuromorphic device including the synaptic device, and operating methods thereof are disclosed. A synaptic device may comprise a channel, a charge trap layer directly contacting the channel, a blocking insulating layer disposed on the charge trap layer, a control electrode disposed on the blocking insulating layer, a first terminal connected to a first region of the channel, and a second terminal connected to a second region of the channel. The synaptic device may change a post-synaptic current (PSC) and control synaptic plasticity according to a control signal applied to the control electrode. The synaptic device may have a SONS (doped poly-silicon/blocking oxide/charge trap nitride/silicon channel) structure. The synaptic device may have SADP characteristics, SDDP characteristics, SFDP characteristics, SNDP characteristics, and STDP characteristics.

Abstract: A secondary battery may include a cell body member accommodating an electrode assembly therein; and a heat conductive member disposed between the cell body member and a cooling plate member to form a heat path for transferring heat from the cell body member, wherein the heat conductive member is in contact with the cooling plate member, and wherein a contact area of the cooling plate member and the heat conductive member is smaller than a cross-sectional area of the cell body member parallel to a thickness direction of the electrode assembly.

Abstract: A nonvolatile memory device and an operating method thereof are disclosed. An operating method of a nonvolatile memory device may comprise providing the nonvolatile memory device including a memory transistor, the memory transistor including a source, a drain, a channel disposed between the source and the drain, and a first insulating layer, a charge storage layer, a second insulating layer, and a gate which are sequentially disposed on the channel, and curing the memory transistor by removing charges or traps existing at least at an interface between the channel and the first insulating layer by generating a gate induced drain leakage (GIDL) current on the drain side of the memory transistor and using Joule heating caused by the GIDL current.

Abstract: A battery module including a cell stack including a plurality of battery cells that are stacked on top of one another, the plurality of battery cells including electrode leads, at least one bus bar structured to provide a plurality of through-slits into which the electrode leads are inserted, and a bus bar frame coupled to the at least one bus bar, the bus bar frame having a plurality of through-holes in which the electrode leads are disposed. Each of the through-slits may include a first guide portion structured to include a first space wider than a width of a corresponding through-slit for a corresponding electrode lead to be inserted toward the through-slit, and the bus bar frame may include a second guide portion structured to include a second space that extends from the first space and has a width wider than the first space.

Abstract: A battery module according to an embodiment of the present disclosure includes a plurality of secondary battery cells; and a housing member including a cooling plate member, and a heat conductive member provided between the secondary battery cells and the cooling plate member to form a heat path for transferring heat from the secondary battery cells to the cooling plate member, the housing member having the plurality of secondary battery cells accommodated therein, wherein the heat conductive member is comprised such that a portion of the heat conductive member in contact with a secondary battery cell that is supercooled has a lower thermal conductivity than a remaining portion of the heat conductive member.

Abstract: A battery cell assembly includes a first battery cell, a second battery cell disposed to face the first battery cell, a protective member disposed between the first battery cell and the second battery cell, and a support member coupled to at least one side of the protective member and supporting the protective member. The protective member includes a heat insulating member preventing heat propagation between the first battery cell and the second battery cell.

Abstract: A battery pack includes a pack housing including a lower frame and a side frame; and one or more battery modules accommodated in the pack housing. The battery module includes a plurality of cell stacks in which a plurality of battery cells are stacked in a first direction; and a plurality of end plates fastened to the lower frame. The plurality of end plates and the plurality of cell stacks are alternately disposed in the first direction.

Abstract: A battery pack includes a cell assembly; and a pack case accommodating the cell assembly in an internal space, wherein the pack case includes a lower plate having a plate shape and a frame disposed to protrude upwardly from the lower plate, wherein the frame has an inlet through which flame flows from the cell assembly into the internal space of the frame, and a flow path through which the flame flowing in from the inlet flows, wherein the flow path is formed by a partition wall disposed in the length direction of the frame, and wherein at least two or more of the partition walls are spaced apart from each other in the height direction of the frame such that a direction of the flow path is able to be changed.

Abstract: A battery pack may include a pack housing including an accommodation space and a venting passage connecting the accommodation space to outside, a partition wall member partitioning the accommodation space, a plurality of pack units including battery cells, the plurality of pack units disposed in the accommodation space, and a blocking unit provided between the accommodation space and the venting passage, the blocking unit blocking a substance generated in the pack unit from entering the venting passage.

Abstract: A battery module includes a cell stack in which a plurality of battery cell assemblies are stacked; a busbar assembly electrically connected to the cell stack; and a cover assembly covering the busbar assembly, wherein at least one of the plurality of battery cell assemblies includes at least two battery cells opposing each other; and a support member supporting the at least two battery cells, and wherein the busbar assembly is coupled to the support member.

Abstract: A battery pack includes a pack housing having an internal space; and a battery module including a plurality of battery cells and accommodated in the internal space, wherein the pack housing includes a support frame opposing at least one side of the battery module and having a venting passage formed therein, and wherein the support frame includes a plurality of guide blocks inserted into the battery module; and an opening disposed between the plurality of guide blocks and communicating with the venting passage and the internal space.

Abstract: A battery device includes a plurality of cell assemblies each including a plurality of battery cells; a housing including an accommodation space in which the plurality of cell assemblies are accommodated; and a cooling plate installed in the housing to cool the plurality of cell assemblies, wherein the cooling plate includes a plurality of seating portions on which the cell assemblies are seated, respectively, and a heat transfer delay portion disposed between the plurality of seating portions and preventing or reducing heat transfer between the seating portions adjacent to each other.

Abstract: A battery pack includes at least one battery module; and a pack housing having an internal space in which the battery module is accommodated, wherein the at least one battery module includes a cell stack including a plurality of battery cells; and an upper cover covering an upper surface of the cell stack and coupled to the pack housing.

Abstract: A battery pack includes a plurality of battery modules each including a plurality of battery cells; and a pack housing having a plurality of accommodation spaces in which the plurality of battery modules are accommodated, wherein the pack housing includes a plurality of venting holes disposed on an external surface of the pack housing and configured to discharge gas generated from the plurality of battery modules, and wherein each of the plurality of accommodation spaces is configured to communicate with a different venting hole among the plurality of venting holes.

Abstract: A bus bar includes terminal portions disposed at both ends, respectively; a plurality of bridges disposed between the terminal portions to electrically connect the terminal portions, and to be sequentially fused when an overcurrent flows. The plurality of bridges may be configured to have different resistance values, respectively.