Abstract: A battery module includes a plurality of battery sub-packing units including at least one battery cell and a case in which the at least one battery cell is accommodated, and a body frame unit surrounding upper portions and outermost side portions of the plurality of battery sub-packing units, where lower portions of the plurality of battery sub-packing units are directly exposed to the outside.

Abstract: A battery sub-packing unit includes at least one battery cell; and a case accommodating the at least one battery cell, wherein the case comprises an end panel on which an electrode tab of the at least one battery cell is fastened to extend into an external space, and having a lower end portion in which a sub-vent hole is formed for communication between the external space and an internal space in which the at least one battery cell is disposed.

Abstract: A battery module includes: a plurality of battery sub-packing units including at least one battery cell and a case in which the at least one battery cell is accommodated; and a body frame unit in which the plurality of battery sub-packing units are installed, the body frame unit surrounding the plurality of battery sub-packing units to be isolated, wherein the case may include a sub vent hole for allowing communication between an interior of the case and an exterior of the case in which the at least one battery cell is disposed.

Abstract: A pouch-type battery cell includes an electrode assembly, a pouch having at least one electrode accommodation portion accommodating the electrode assembly therein and a sealing portion for sealing the electrode assembly, and electrode leads electrically connected to the electrode assembly and exposed externally of the pouch through the sealing portion, wherein the electrode accommodation portion includes a body portion of which a width is greater than a height thereof, and an extension portion extending from a central portion of the body portion in a width direction to one side and having a width narrower than the width of the body portion, the electrode leads are disposed outside the extension portion in the width direction, and an end of the electrode leads has a height lower than an outer portion of the pouch.

Abstract: A battery module includes a plurality of pouch-type battery cells, each of the pouch-type battery cells including an electrode assembly, a pouch, and electrode leads, the pouch including at least one electrode accommodation portion and a sealing portion; and a bus bar assembly having at least one conductive bus bar, wherein the electrode accommodation portion includes a body portion having a width greater than a height thereof, and an extension portion extending in a height direction and protruding from a central portion of the body portion, wherein the electrode leads are extending in the height direction, wherein the bus bar is coupled to the electrode leads in a vertical direction of the pouch-type battery cell, and wherein the upper end of the bus bar in the height direction is lower than an upper end of an extension portion of the pouch.

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Abstract: A bus bar includes terminal portions disposed at both ends, respectively; a plurality of bridges disposed between the terminal portions to electrically connect the terminal portions, and to be sequentially fused when an overcurrent flows. The plurality of bridges may be configured to have different resistance values, respectively.

Abstract: A structure and an operation of a transistor, which is a vertical transistor in which a nanowire-type floating body layer is vertically formed or a horizontal transistor in which a floating body layer is horizontally formed, and implements a spike operation of a neuron by storing and releasing charges inside the transistor, and a neuromorphic system using the same are provided. The vertical transistor includes a floating body layer in a form of a vertical nanowire vertically formed on a substrate, a source and a drain formed above and below the floating body layer, a gate insulating layer formed on the source and surrounding the floating body layer, a gate formed outside the gate insulating layer, and a contact metal being in contact with the source, the drain and the gate to input or output an electrical signal.

Abstract: A battery cell includes a casing having an accommodation space formed therein and having one or both ends open; a cover plate covering one or both open ends of the casing; and an electrode assembly accommodated in the accommodation space, in which a plurality of electrode plates are stacked with a separator interposed therebetween. The electrode assembly includes electrode connection portions, respectively extending from the plurality of electrode plates; and a terminal bonded to the electrode connection portion and having a portion exposed outwardly through the cover plate.

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (?) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

Abstract: A bus bar includes terminal portions disposed at both ends, respectively; a plurality of bridges disposed between the terminal portions to electrically connect the terminal portions, and to be sequentially fused when an overcurrent flows. The plurality of bridges may be configured to have different resistance values, respectively.

Abstract: A battery pack includes a plurality of cell stack units, each stack unit including a stack of a plurality of battery cells, a partition wall member disposed between the cell stack units adjacent to each other, and a pack housing accommodating the plurality of cell stack units and a plurality of partition wall members. The cell stack unit and the partition wall member are accommodated in the pack housing while side surface of the cell stack unit and a side surface of the partition wall member are in contact with each other, and the partition wall member is fixed to a bottom surface of the pack housing.

Abstract: Disclosed is an ion controllable transistor-based neuromorphic synaptic device used for a memory and a neuromorphic computing in such a manner that a synaptic weight is analogically updated and maintained. The ion controllable transistor-based neuromorphic synaptic device includes a channel area formed on a semiconductor substrate; a source area and a drain area formed at both sides of the channel area, respectively; an interlayer insulating film provided on the channel area; a gate area formed on the interlayer insulating film; and a solid electrolyte layer inserted between the interlayer insulating film and the gate area.

Abstract: A neuromorphic synaptic device based on a charge trap and having linearity and symmetricity improved by using a schottky junction and a neuromorphic system using the same are provided. The neuromorphic synaptic device includes a body layer formed on a semiconductor substrate, a source and a drain formed at a left side and a right side, or an upper side and a lower side of the body layer, a contact metal to form a schottky junction by making contact with the source and the drain, a gate insulating layer formed on the body layer, and including an oxide layer and a charge storage layer, and a gate formed on the gate insulating layer.

Abstract: Disclosed is a single transistor with a double gate structure for an adjustable firing threshold voltage and a neuromorphic system using the same. A single transistor neuron with a double gate structure according to an example embodiment includes a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer; a source and a drain formed at both sides of the floating body layer, respectively; a driving gate formed at a first side of the floating body layer without contacting the source and the drain; a control gate formed at a second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate.

Abstract: A battery module includes: a plurality of secondary battery cells; and a housing unit having an internal space in which the plurality of secondary battery cells are accommodated and including a plate member extending a flame or gas path.

Abstract: A battery module which may prevent or delay a short circuit with respect to nail penetration includes a cell assembly including a plurality of cells electrically connected to each other, an outer case of the battery module, covering the cell assembly, and an elastic refractory material provided in a region between the outer case of the battery module and an outermost cell of the cell assembly or a region between one of the cells and an adjacent cell in the battery module, wherein the elastic refractory material includes an elastic layer and a heat conductive layer.

Abstract: Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path.

Abstract: A battery module includes a plurality of secondary battery cells, a housing member accommodating a plurality of the secondary battery cells therein, and an insulating member disposed on an inner surface of the housing member, preventing flow of electrical current to the housing member, having a heat transfer function to discharge heat of the secondary battery cell externally, and formed to have a predetermined thickness.

Abstract: The present invention relates to a single transistor implementing a neuromorphic system capable of performing neuron and synaptic operations through the single transistor including a floating body layer and a charge storage layer and being implemented by a neuron device and a synaptic device which are co-integrated on the same plane, and the neuromorphic system using the same, and forms the single transistor including a hole barrier material layer formed on a substrate and including a hole barrier material or an electron barrier material, the floating body layer formed on the hole barrier material layer, a source and a drain formed on opposite sides of the floating body layer, a gate insulating layer formed on the floating body layer and including an oxide layer and the charge storage layer, and a gate formed on the gate insulating layer.