Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.

Abstract: A secondary battery may include a cell body member accommodating an electrode assembly therein and provided adjacently to a cooling plate member; and a heat conductive member provided in at least a portion between the cell body member and the cooling plate member to form a heat path for transferring heat from the cell body member. The cell body member, in contact with the heat conductive member on a lower surface thereof, includes a surface area-increasing groove formed to be concave in the lower surface thereof.

Abstract: A secondary battery may include a cell body member accommodating an electrode assembly therein; and a heat conductive member disposed between the cell body member and a cooling plate member to form a heat path for transferring heat from the cell body member, wherein the heat conductive member is in contact with the cooling plate member, and wherein a contact area of the cooling plate member and the heat conductive member is smaller than a cross-sectional area of the cell body member parallel to a thickness direction of the electrode assembly.

Abstract: A battery module according to an embodiment of the present disclosure includes a plurality of secondary battery cells; and a housing member including a cooling plate member, and a heat conductive member provided between the secondary battery cells and the cooling plate member to form a heat path for transferring heat from the secondary battery cells to the cooling plate member, the housing member having the plurality of secondary battery cells accommodated therein, wherein the heat conductive member is comprised such that a portion of the heat conductive member in contact with a secondary battery cell that is supercooled has a lower thermal conductivity than a remaining portion of the heat conductive member.

Abstract: A structure and an operation of a transistor, which is a vertical transistor in which a nanowire-type floating body layer is vertically formed or a horizontal transistor in which a floating body layer is horizontally formed, and implements a spike operation of a neuron by storing and releasing charges inside the transistor, and a neuromorphic system using the same are provided. The vertical transistor includes a floating body layer in a form of a vertical nanowire vertically formed on a substrate, a source and a drain formed above and below the floating body layer, a gate insulating layer formed on the source and surrounding the floating body layer, a gate formed outside the gate insulating layer, and a contact metal being in contact with the source, the drain and the gate to input or output an electrical signal.

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Abstract: Disclosed are a clamping device and a battery module comprising the same, the clamping device being suitable for reducing the number of screw coupling portions of long bolts at a lower plate, a battery stack, and an upper plate, and for securing, in a balanced manner, the battery stack, the lower plate and the upper plate by means of the long bolts. The clamping device according to the present invention comprises: a support; and pressing parts respectively protruded from one end and the other end of the support, wherein the support and the pressing parts define a bent part along the central portion of the outer circumference while forming a band shape, and the pressing parts include locking holes which intersect with the bent portion.

Abstract: Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path.

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

Abstract: Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer.

Abstract: A bus bar includes terminal portions disposed at both ends, respectively; a plurality of bridges disposed between the terminal portions to electrically connect the terminal portions, and to be sequentially fused when an overcurrent flows. The plurality of bridges may be configured to have different resistance values, respectively.

Abstract: The present disclosure discloses a battery pack suitable for preventing simultaneous separation of both ends of a handle unit from an upper case during transportation of a lower case and the upper case that are laminated sequentially. The battery pack according to the present disclosure includes the lower case and the upper case stacked sequentially to encase a battery module, wherein the upper case includes a housing and a handle unit relatively rotated with respect to the housing to be seated on the housing, and the handle unit has shaft hooks that are penetrated by the rotation supporting shafts of the housing and that are each rotary-coupled to each of the rotation supporting shafts in different angles.

Abstract: Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer.

Abstract: Provided is a battery module including: a battery cell assembly including a plurality of battery cells stacked with one another; end plates configured to cover front and rear portions of the battery cell assembly and to be coupled to the battery cell assembly at a side of each of the end plates; and a fixing holder configured to be mounted to a battery cell assembly at an opposite side of each of the end plates in order to at least partially cover the battery cell assembly, and to protrude from front and rear portions of the end plates.

Abstract: The present disclosure discloses a pack case suitable for preventing vibration or deviation of a battery module on a case during an assembly operation, and a battery pack including the same. The pack case according to the present disclosure includes an align unit and a bus bar disposed at an edge on an inner circumferential surface, and a main case having a connection terminal contacting the bus bar on an outer circumferential surface, and the align unit and the bus bar contact a battery module at a periphery of the battery module seated on the inner circumferential surface of the main case.

Abstract: Provided is a bus bar structure which may be suitable for reducing an occupied area of a printed circuit board (PCB) by removing a fuse from the PCB in an interconnect board (ICB) assembly of a battery pack. According to the present disclosure, the bus bar structure may include: bus bars which face each other and are arranged below the PCB in the ICB assembly of the battery pack; and a fuse case between the bus bars, wherein the fuse case includes a fuse wire therein and is configured to bring the fuse wire into contact with the bus bars via at least one end thereof.

Abstract: The present disclosure discloses a battery pack that realizes miniaturization and weight reduction by minimizing the number of components of the structure, and that is suitable for pursuing dispersion of external force and structural rigidity using the shape of the structure. The battery pack according to the present disclosure is characterized to include a lower case including both inclined side walls and fixating members facing each other at the both side walls, a battery cartridge disposed between the fixating members in the lower case, and an upper case covering the lower case and the battery cartridge, wherein the battery cartridge contacts the both side walls and the fixating members in the lower case.

Abstract: The present invention provides a battery module, which includes: a battery group formed by stacking a plurality of battery cells, each of which includes electrode tabs; a cooling housing including a cooling plate located corresponding to one side of sides of the battery group, in which the electrode tabs are not extended, and side plates located on both sides of the battery group perpendicular to the one side of the sides, thus to house the battery group; a cover plate located on the other side of the battery group; and a front cover part and a rear cover part, which are located at outermost front and rear of the battery group on both sides in a direction in which the electrode tabs are extended.

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (?) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.